Image sensor
An example embodiment provides an image sensor including: a pixel array including a first floating diffusion and a second floating diffusion, the first floating diffusion and the second floating diffusion configured to store charges generated by a first phase detecting pixel and a second phase detecting pixel adjacent to each other in a first direction and covered with one micro lens, and the pixel array is configured to output a first signal based on a charge that is generated by the first phase detecting pixel to be accumulated in the first floating diffusion and the second floating diffusion; and a row driver configured to apply a boosting control signal to the second floating diffusion to transfer charges stored in the second floating diffusion to the first floating diffusion, after the pixel array outputs the first signal.
1. An image sensor comprising:
a pixel array including a first floating diffusion and a second floating diffusion, the first floating diffusion and the second floating diffusion configured to store charges generated by a first phase detecting pixel and a second phase detecting pixel, the first phase detecting pixel and the second phase detecting pixel adjacent to each other in a first direction and covered with one micro lens, and the pixel array is configured to output a first signal based on a charge that is generated by the first phase detecting pixel to be accumulated in the first floating diffusion and the second floating diffusion; and
a row driver configured to apply a boosting control signal to the second floating diffusion to transfer charges stored in the second floating diffusion to the first floating diffusion, after the pixel array outputs the first signal.
2. The image sensor of claim 1 , wherein
the second floating diffusion includes a silicon layer, and an electrode positioned on the silicon layer, and
the electrode is configured to have the boosting control signal applied thereto.
3. The image sensor of claim 1 , wherein
after the row driver applies the boosting control signal, the pixel array is configured to output a second signal based on charges generated by the first phase detecting pixel and the second phase detecting pixel accumulated in the first floating diffusion.
4. The image sensor of claim 3 , wherein
before the first signal is outputted, the pixel array is configured to output a third signal based on a charge that is generated by the first phase detecting pixel to be accumulated in the first floating diffusion.
5. The image sensor of claim 4 , wherein
after the second signal is outputted, the pixel array is configured to output a fourth signal based on charges that are generated by the first phase detecting pixel and the second phase detecting pixel to be accumulated in the first floating diffusion and the second floating diffusion.
6. The image sensor of claim 2 , wherein
the pixel array further includes a switch transistor connected between the first floating diffusion and the second floating diffusion, and the row driver is configured to control the switch transistor such that the boosting control signal is applied to the second floating diffusion while the switch transistor is turned on after the pixel array outputs the first signal.
7. The image sensor of claim 6 , wherein
the row driver is configured to apply the boosting control signal to the second floating diffusion while the pixel array outputs a second signal.
8. A pixel comprising:
a first phase detecting pixel connected to a first node;
a second phase detecting pixel connected to a first node and disposed adjacent to the first phase detecting pixel;
a first floating diffusion configured to determine a voltage of the first node based on charges generated by the first phase detecting pixel and the second phase detecting pixel;
a second floating diffusion connected to the first node; and
a driving transistor configured to receive a control signal such that the driving transistor sequentially outputs a first signal based on a charge generated by the first phase detecting pixel to be accumulated in the first floating diffusion, a second signal based on a charge generated by the first phase detecting pixel to be accumulated in the first floating diffusion and the second floating diffusion, and a third signal based on charges generated by the first phase detecting pixel and the second phase detecting pixel to be accumulated in the first floating diffusion.
9. The pixel of claim 8 , wherein
the second floating diffusion includes a silicon layer, and an electrode that is positioned on the silicon layer and
the electrode is configured to have a boosting control signal applied thereto.
10. The pixel of claim 9 , wherein
the second floating diffusion is configured to receive the boosting control signal to transfer a charge stored in the second floating diffusion to the first floating diffusion after the driving transistor outputs the second signal.
11. The pixel of claim 10 , wherein
the driving transistor is configured to receive the control signal such that the driving transistor outputs the third signal after the boosting control signal is applied.
12. The pixel of claim 8 , wherein
the driving transistor is configured to receive the control signal such that, after the third signal is outputted, the driving transistor further outputs a fourth signal based on charges that are generated by the first phase detecting pixel and the second phase detecting pixel to be accumulated in the first floating diffusion and the second floating diffusion.
13. The pixel of claim 9 , further comprising
a switch transistor connected between the first floating diffusion and the second floating diffusion,
wherein the second floating diffusion is configured to receive the boosting control signal to transfer a charge stored in the second floating diffusion to the first floating diffusion while the switch transistor is turned on after the driving transistor outputs the second signal.
14. The pixel of claim 13 , wherein
the second floating diffusion is configured to receive the boosting control signal while the third signal is output.
15. The pixel of claim 14 , wherein
the driving transistor is configured to receive the control signal such that, after the third signal is outputted, the driving transistor further outputs a fourth signal based on charges that are generated by the first phase detecting pixel and the second phase detecting pixel to be accumulated in the first floating diffusion and the second floating diffusion.
16. An image sensor comprising:
a semiconductor substrate in which a plurality of pixel areas are defined;
a first photoelectric element provided inside the semiconductor substrate in each of the plurality of pixel areas, and a second photoelectric element adjacent to the first photoelectric element;
a first transmission transistor having a transmission gate electrode having at least a partial area buried in the semiconductor substrate and the transmission gate electrode extending in a direction perpendicular to the first photoelectric element;
a second transmission transistor having a transmission gate electrode having at least a partial area buried in the semiconductor substrate to extend in a direction perpendicular to the second photoelectric element;
a first floating diffusion configured to accumulate charges transferred from the first photoelectric element and the second photoelectric element via the first transmission transistor and the second transmission transistor;
a second floating diffusion including a silicon layer, and an electrode positioned on the silicon layer and configured to receive a boosting control signal, and transfer charges transferred from the first photoelectric element and the second photoelectric element to the first floating diffusion in response to the boosting control signal being applied.
17. The image sensor of claim 16 , wherein
the second floating diffusion includes a contact that is positioned on the silicon layer and is connected to a wire connected to the first floating diffusion.
18. The image sensor of claim 16 , wherein
the first floating diffusion is positioned in an area in which the silicon layer of the second floating diffusion extends.
19. The image sensor of claim 18 , further comprising
a switch transistor positioned between the first floating diffusion and the second floating diffusion.
20. The image sensor of claim 16 , wherein
the semiconductor substrate includes polysilicon,
the first floating diffusion includes a p-type of well area, and the second floating diffusion includes a well area, and the well area includes the polysilicon.