Two-dimension self-aligned scheme with subtractive metal etch
Methods for formation of a layer stack during a back-end-of-line (BEOL) process flow and the layer stack formed therefrom are provided. In one or more embodiments, the method utilizes a two-dimensional (2D) self-aligned scheme with a subtractive metal etch. The method includes using a hard mask to form a via with a small width which is formed through or contacts each of a first metal layer and a second metal layer. The via is filled with a metal gapfill to connect the first metal layer and the second metal layer. Each of the first metal layer and the second metal layer are patterned to form a plurality of features.
1. A method of processing a substrate, suitable for semiconductor manufacturing, comprising:
depositing a first oxide layer over a patterned hard mask layer;
etching a first portion of a via through the first oxide layer and through an opening within the patterned hard mask layer;
etching a second portion of the via through an upper metal layer and one or more low-k material layers to expose a portion of a lower metal layer, the one or more low-k material layers disposed between the upper metal layer and the lower metal layer;
gap-filling the second portion of the via with a gapfill metal;
filling the first portion of the via with a second oxide layer;
removing a portion of the first oxide layer and the second oxide layer to form a patterned layer;
removing the patterned hard mask layer to form openings within the patterned layer; and
etching a portion of the upper metal layer through the openings within the patterned layer after removing the patterned hard mask layer.
2. The method of claim 1 , wherein a first hard mask is disposed between the lower metal layer and the one or more low-k material layers and a second hard mask is disposed between the upper metal layer and the patterned hard mask layer.
3. The method of claim 2 , wherein the first hard mask layer and the second hard mask layer are silicon nitride layers.
4. The method of claim 1 , wherein the patterned hard mask layer is a titanium nitride or a tungsten carbide hard mask.
5. The method of claim 1 , wherein the first portion of the via has a first width of about 15 nm to about 25 nm.
6. The method of claim 1 , wherein the patterned hard mask layer comprises a plurality of features and each feature is separated by a second width of less than 15 nm.
7. The method of claim 6 , wherein the second portion of the via is disposed between two adjacent features of the plurality of features.
8. The method of claim 1 , wherein each of the upper metal layer, the lower metal layer, and the gapfill metal are the same.
9. The method of claim 8 , wherein each of the upper metal layer, the lower metal layer, and the gapfill metal comprises ruthenium, molybdenum, tungsten, alloys thereof, or any combination thereof.
10. A method of processing a substrate, suitable for semiconductor manufacturing, comprising:
depositing a low temperature oxide layer over a patterned hard mask layer, the patterned hard mask layer comprising a plurality of openings and the low temperature oxide layer disposed within the plurality of openings;
etching a first portion of a via through the low temperature oxide and through an opening within the patterned hard mask layer;
etching a second portion of the via through an upper metal layer, an insulating layer, a low-k layer, and a blocking layer to expose a portion of a lower metal layer; and
gap-filling the second portion of the via with a gapfill metal to connect the upper metal layer and the lower metal layer.
11. The method of claim 10 , further comprising:
filling the first portion of the via with a second low temperature oxide after gap-filling the second portion;
removing a portion of the low temperature oxide layer and the second low temperature oxide to form a patterned layer, wherein the low temperature oxide layer is disposed within gaps of the patterned hard mask layer;
removing the patterned hard mask layer; and
etching a portion of the upper metal layer through openings within the low temperature oxide layer after removing the patterned hard mask layer.
12. The method of claim 10 , wherein the insulating layer is a Tetraethyl orthosilicate layer.
13. The method of claim 10 , wherein the low-k layer has a dielectric constant of less than 4.
14. The method of claim 13 , wherein the low-k layer comprises a silicon oxycarbide.
15. The method of claim 10 , wherein the first portion of the via has a first width of about 15 nm to about 25 nm and the second portion of the via has a second width less than the first width and the second width is less than 15 nm.
16. The method of claim 10 , wherein a photoresist layer is disposed over the low temperature oxide layer and is patterned, such that etching the via is performed through a portion of the photoresist layer.
17. The method of claim 10 , wherein the blocking layer is an aluminum oxide layer.