Printed circuit board and a semiconductor package including the same
A printed circuit board includes a substrate structure including a first insulating material, a plurality of first wiring layers disposed on or in the first insulating material, and a plurality of first via layers disposed in the first insulating material; and an interconnect structure including a second insulating material, a plurality of second wiring layers disposed on or in the second insulating material, and one or more second via layers disposed in the second insulating material. The interconnect structure is disposed on an upper side of the substrate structure. The interconnect structure includes first and second connection regions. The first and second connection regions are spaced apart from each other.
1. A printed circuit board, comprising:
a substrate structure including a first insulating material, a plurality of first wiring layers disposed on or in the first insulating material, and a plurality of first via layers disposed in the first insulating material; and
an interconnect structure including a second insulating material, a plurality of second wiring layers disposed on or in the second insulating material, and one or more second via layers disposed in the second insulating material,
wherein an upper surface of the second insulating material is exposed from an upper surface of the first insulating material, and at least a portion of each of a lower surface and a side surface of the second insulating material is covered with the first insulating material,
wherein the interconnect structure is disposed on an upper side of the substrate structure,
wherein the interconnect structure includes first and second connection regions, and
wherein the first and second connection regions are spaced apart from each other.
2. The printed circuit board of claim 1 , wherein the first and second connection regions include different portions of the plurality of second wiring layers and different portions of the one or more second via layers, respectively.
3. The printed circuit board of claim 1 ,
wherein the interconnect structure further includes third to fifth connection regions, and
wherein the first to fifth connection regions are spaced apart from each other.
4. The printed circuit board of claim 3 , wherein the first to fifth connection regions include different portions of the plurality of second wiring layers and different portions of the one or more second via layers, respectively.
5. The printed circuit board of claim 1 , wherein an average pitch of wirings included in the plurality of second wiring layers is smaller than an average pitch of wirings included in the plurality of first wiring layers.
6. The printed circuit board of claim 5 , wherein an average interlayer insulation distance between the plurality of second wiring layers is smaller than an average interlayer insulation distance between the plurality of first wiring layers.
7. The printed circuit board of claim 1 , wherein a second wiring layer disposed on an uppermost side of the plurality of second wiring layers is embedded in an upper side of the second insulating material and has an upper surface exposed from an upper surface of the second insulating material.
8. The printed circuit board of claim 1 , wherein the second insulating material has a planar area smaller than that of the first insulating material.
9. The printed circuit board of claim 1 ,
wherein a first wiring layer disposed on an uppermost side of the plurality of first wiring layers and a first via layer disposed on an uppermost side of the plurality of first via layers are disposed around the second insulating material, and
wherein the first wiring layer disposed on the uppermost side of the plurality of first wiring layers is embedded in an upper side of the first insulating material and has an upper surface exposed from the upper surface of the first insulating material.
10. The printed circuit board of claim 1 ,
wherein the first insulating material includes a plurality of first insulating layers laminated on an upper side and a plurality of second insulating layers laminated on a lower side, and
wherein the plurality of first and second insulating layers include different insulating materials.
11. The printed circuit board of claim 10 , wherein each of the second insulating layers has an elastic modulus greater than that of each of the first insulating layers.
12. The printed circuit board of claim 1 ,
wherein the first and second connection regions are not connected to each other in the interconnect structure.
13. A printed circuit board, comprising:
a substrate structure including a first insulating material, a plurality of first wiring layers disposed on or in the first insulating material, and a plurality of first via layers disposed in the first insulating material; and
an interconnect structure including a second insulating material, a plurality of second wiring layers disposed on or in the second insulating material, and one or more second via layers disposed in the second insulating material,
wherein the interconnect structure is disposed on an upper side of the substrate structure,
wherein the interconnect structure includes first and second connection regions, wherein the first and second connection regions are spaced apart from each other, and
wherein at least a portion of a lower surface of the second insulating material is covered with the first insulating material, and a side surface of the second insulating material is exposed from the first insulating material.
14. The printed circuit board of claim 13 , wherein the first and second insulating materials have substantially the same planar area.
15. A semiconductor package, comprising:
a printed circuit board including a substrate structure and an interconnect structure disposed on an upper side of the substrate structure, where the interconnect structure includes first and second connection regions including a wiring layer and a via layer, respectively, and the first and second connection regions are spaced apart from each other;
a first semiconductor chip mounted on the printed circuit board;
a second semiconductor chip mounted on the printed circuit board and connected to the first semiconductor chip through the first connection region; and
a third semiconductor chip mounted on the printed circuit board and connected to the first semiconductor chip through the second connection region,
wherein the substrate structure comprises a plurality of first insulating layers and the interconnection structure comprises a plurality of second insulating layers having different materials,
wherein at least a portion of each of a lower surface and side surface of at least one of the plurality of second insulating layers is covered with a corresponding of the plurality of first insulating layers.
16. The semiconductor package of claim 15 ,
wherein the interconnect structure further includes third to fifth connection regions, and
wherein the first to fifth connection regions are spaced apart from each other.
17. The semiconductor package of claim 16 ,
wherein the substrate structure includes a plurality of wiring layers and a plurality of via layers, and
wherein the first to third semiconductor chips are connected to different portions of the plurality of wiring layers of the substrate structure through the third to fifth connection regions, respectively.
18. The semiconductor package of claim 15 , wherein the interconnect structure provides an outermost mounting surface of the printed circuit board on which the first to third semiconductor chips are mounted.
19. A printed circuit board, comprising:
a substrate structure including a first insulating material, a plurality of first wiring layers disposed on or in the first insulating material, and a plurality of first via layers disposed in the first insulating material; and
an interconnect structure including a second insulating material, a plurality of second wiring layers disposed on or in the second insulating material, and one or more second via layers disposed in the second insulating material,
wherein a side surface of an uppermost portion of the second insulating material is in contact with the first insulating material,
wherein one or more vias of the plurality of first via layers extends from one of the plurality of second wiring layers, and
wherein the first insulating material and the second insulating material provide portions of an outermost surface of the printed circuit board.
20. The printed circuit board of claim 19 , wherein an average pitch of wirings included in the plurality of second wiring layers is smaller than an average pitch of wirings included in the plurality of first wiring layers.
21. The printed circuit board of claim 19 , wherein an average interlayer insulation distance between the plurality of second wiring layers is smaller than an average interlayer insulation distance between the plurality of first wiring layers.
22. The printed circuit board of claim 19 ,
wherein the first insulating material includes a plurality of insulating layers and the second insulating material includes a plurality of insulating layers, and
wherein an uppermost insulating layer of the first insulating material and an uppermost insulating layer of the second insulating material are coplanar with each other.
23. The printed circuit board of claim 22 ,
wherein an uppermost wiring layer of the plurality of first wiring layers and an uppermost wiring layer of the plurality of second wiring layers are coplanar with the uppermost insulating layer of the first insulating material and the uppermost insulating layer of the second insulating material.