Middle-of-line interconnect structure and manufacturing method
In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure includes a gate electrode separated from a substrate by a gate dielectric and a pair of source/drain regions disposed within the substrate on opposite sides of the gate electrode. A lower conductive plug is disposed through a lower inter-layer dielectric (ILD) layer and contacting a first source/drain region. A capping layer is disposed directly on the lower conductive plug. An upper inter-layer dielectric (ILD) layer is disposed over the capping layer and the lower ILD layer. An upper conductive plug is disposed through the upper ILD layer and directly on the capping layer.
1. An integrated circuit device, comprising:
a lower inter-layer dielectric (ILD) layer disposed over a substrate;
a lower conductive plug disposed in the lower ILD layer;
an upper ILD layer disposed over the lower ILD layer; and
an upper conductive plug disposed in the upper ILD layer and comprising a metal core and an intermixing barrier layer disposed along sidewall surfaces of the metal core;
wherein the intermixing barrier layer comprises a material of the metal core and a material of the upper ILD layer, and wherein a bottommost surface of the metal core extends beneath a bottommost surface of the intermixing barrier layer.
2. The integrated circuit device of claim 1 , wherein the bottommost surface of the metal core overlies a topmost surface of the lower ILD layer.
3. The integrated circuit device of claim 1 , further comprising a first etch stop layer, wherein the bottommost surface of the intermixing barrier layer is on an upper surface of the first etch stop layer.
4. The integrated circuit device of claim 3 , wherein the first etch stop layer directly contacts the metal core along the sidewall surfaces of the metal core beneath the intermixing barrier layer.
5. The integrated circuit device of claim 1 , further comprising a gate, the gate comprising:
a gate electrode over the substrate;
a gate dielectric extending between the gate electrode and the substrate; and
a gate barrier layer covering an upper surface of the gate electrode, wherein the upper conductive plug contacts the gate barrier layer.
6. The integrated circuit device of claim 1 , further comprising:
a first etch stop layer separating the lower ILD layer and the upper ILD layer; and
a lower barrier layer surrounding the lower conductive plug, wherein an upper surface of the lower barrier layer is level with an upper surface of the first etch stop layer.
7. The integrated circuit device of claim 6 , further comprising a capping layer covering an upper surface of the lower conductive plug, the capping layer confined between inner sidewalls of the lower barrier layer and having an upper surface substantially coplanar with the upper surface of the lower barrier layer and the upper surface of the first etch stop layer.
8. An integrated device, comprising:
a lower inter-layer dielectric (ILD) layer disposed over a substrate;
a lower conductive plug disposed in the lower ILD layer and comprising a lower conductive core and a lower barrier layer;
an upper ILD layer disposed over the lower ILD layer and having a first bottommost surface;
an upper conductive plug disposed in the upper ILD layer and comprising an upper conductive core and an intermixing barrier layer disposed along sidewall surfaces of the upper conductive core, wherein the upper conductive core has a first lower surface level with the first bottommost surface, and wherein the intermixing barrier layer has a second bottommost surface level with the first bottommost surface; and
a capping layer comprising a different material from the lower conductive core and the upper conductive core and spacing a first upper surface of the lower conductive core from the first lower surface of the upper conductive core;
wherein the lower barrier layer comprises a second upper surface level with the first bottommost surface.
9. The integrated device of claim 8 , wherein the upper conductive core has a second lower surface extending beneath the first lower surface and a lowermost surface of the intermixing barrier layer.
10. The integrated device of claim 9 , wherein the intermixing barrier layer extends from an uppermost surface of the upper conductive core to the first lower surface of the upper conductive core.
11. The integrated device of claim 9 , further comprising a gate on the substrate, wherein the second lower surface of the upper conductive core contacts the gate, and wherein the first lower surface of the upper conductive core contacts the second upper surface of the lower barrier layer.
12. The integrated device of claim 8 , further comprising:
a second upper conductive plug spaced from the lower conductive plug in a direction parallel to an upper surface of the substrate and comprising a second upper conductive core and a second intermixing barrier layer, wherein the capping layer covers the first upper surface of the lower conductive core and is confined between inner sidewalls of the lower barrier layer, wherein the upper conductive core and the intermixing barrier layer directly contact the capping layer, and wherein the second upper conductive plug is level with the capping layer.
13. The integrated device of claim 8 , wherein the upper conductive core comprises ruthenium.
14. The integrated device of claim 8 , wherein the intermixing barrier layer comprises both atoms of a material of the upper conductive core and atoms of a material of the upper ILD layer.
15. An integrated circuit device, comprising:
a lower inter-layer dielectric (ILD) layer disposed over a substrate;
a lower conductive plug disposed in the lower ILD layer and comprising a lower conductive core and a lower barrier layer;
a gate disposed in the lower ILD and comprising a gate electrode, a gate dielectric between the gate electrode and the substrate, and a gate barrier layer covering an uppermost surface of the gate electrode;
an upper ILD layer disposed over the lower ILD layer;
a first etch stop layer disposed between the upper ILD layer and the lower ILD layer, the first etch stop layer extending beneath an uppermost surface of the lower ILD layer to contact the gate barrier layer, wherein the lower barrier layer extends to an uppermost surface of the first etch stop layer and has an upper surface level with the uppermost surface of the first etch stop layer; and
an upper conductive plug disposed in the upper ILD layer and comprising an upper conductive core and an intermixing barrier layer disposed along sidewall surfaces of the upper conductive core;
wherein the upper conductive core extends into the first etch stop layer, and wherein the upper conductive core directly contacts inner sidewalls of the first etch stop layer.
16. The integrated circuit device of claim 15 , wherein the intermixing barrier layer does not extend into the first etch stop layer.
17. The integrated circuit device of claim 15 , wherein a first portion of the sidewall surfaces of the upper conductive core are covered by the intermixing barrier layer, and wherein a second portion of the sidewall surfaces extend beneath the intermixing barrier layer.
18. The integrated circuit device of claim 15 , wherein the upper conductive core contacts the gate barrier layer.
19. The integrated circuit device of claim 15 , wherein the intermixing barrier layer has a lower surface that is level with the upper surface of the lower barrier layer.
20. The integrated circuit device of claim 15 , wherein the intermixing barrier layer has an upper portion with a first material composition and a lower portion with a second material composition different from the first material composition.