Semiconductor structure with selective bottom terminal contacting
A semi-conductor structure with selective bottom terminal contacting is described. The semiconductor device comprises a first metal layer disposed over a substrate; a conductive layer disposed over the first metal layer; and a second metal layer disposed over the conductive layer, the second metal layer embedding a porous structure comprising a plurality of pores that extend substantially perpendicularly from a top surface of the porous structure toward the conductive layer, wherein only a subset of the plurality of pores open onto the conductive layer.
1. A method of fabricating an RC device, comprising:
forming a first metal layer above a substrate;
forming a conductive layer above the first metal layer;
forming a second metal layer above the conductive layer;
forming a first mask layer on top of the second metal layer, the first mask layer having an opening onto the second metal layer;
anodizing the second metal layer to form a porous structure within the second metal layer, the porous structure underlying the opening of the first mask layer onto the second metal layer and comprising a plurality of pores that extend substantially perpendicularly from a top surface of the porous structure toward the conductive layer;
forming a second mask layer over the porous structure, the second mask layer having an opening onto a second area of the porous structure;
etching the bottom ends of a select set of pores of the plurality of pores; and
forming a metal-insulator-metal (MIM) stack in the plurality of pores of the porous structure.
2. The method of claim 1 , wherein the select set of pores correspond to a subset of the plurality of pores of the porous structure.
3. The method of claim 1 , wherein said etching opens the select set of pores onto the conductive layer.
4. The method of claim 1 , wherein a bottom metal layer of the MIM stack contacts the conductive layer through the select set of pores.
5. The method of claim 1 , wherein said etching comprises:
exposing the porous structure to a wet etching solution.
6. The method of claim 5 , wherein prior to said etching, the bottom ends of the select set of pores are plugged up by an oxide of the conductive layer, and wherein exposing the porous structure to the wet etching solution dissolves said oxide.
7. The method of claim 1 , wherein the select set of pores are comprised within the second area of the porous structure.
8. The method of claim 1 , further comprising:
forming an insulating layer on top of the conductive layer, the insulating layer having an opening onto a third area of the conductive layer.
9. The method of claim 8 , wherein the select set of pores open onto the third area of the conductive layer through the opening of the insulating layer.
10. The method of claim 1 , further comprising:
selecting a target resistance for the RC device; and
determining a surface area of the second area of the porous structure as a function of the target resistance.
11. The method of claim 8 , comprising:
selecting a target resistance for the RC device; and
determining a surface area of the third area of the conductive layer as a function of the target resistance.
12. A semiconductor device, comprising:
a first metal layer disposed over a substrate;
a conductive layer disposed over the first metal layer; and
a second metal layer disposed over the conductive layer, the second metal layer embedding a porous structure comprising a plurality of pores that extend substantially perpendicularly from a top surface of the porous structure toward the conductive layer, wherein a first subset of the plurality of pores open onto the conductive layer and a second subset of the plurality of pores are plugged at their bottom ends by an oxide plug of the conductive layer, the oxide plug containing an oxide of the material of the conductive layer, and the oxide plug is not conductive.
13. The semiconductor device of claim 12 , further comprising:
an insulating layer disposed between the conductive layer and the second metal layer, the insulating layer having an opening onto the conductive layer.
14. The semiconductor device of claim 12 , comprising:
a metal-insulator-metal (MIM) stack formed in the plurality of pores of the porous structure, wherein a bottom metal layer of the MIM stack contacts the conductive layer through the subset of open pores.