4H-SiC electronic device with improved short-circuit performances, and manufacturing method thereof
An electronic device includes a semiconductor body of silicon carbide, and a body region at a first surface of the semiconductor body. A source region is disposed in the body region. A drain region is disposed at a second surface of the semiconductor body. A doped region extends seamlessly at the entire first surface of the semiconductor body and includes one or more first sub-regions having a first doping concentration and one or more second sub-regions having a second doping concentration lower than the first doping concentration. Thus, the device has zones alternated to each other having different conduction threshold voltage and different saturation current.
1. A method for manufacturing an electronic device, comprising:
forming a doped region in a semiconductor body of silicon carbide (SiC), the semiconductor body having a first surface and a second surface, the doped region having a first conductivity, extending seamlessly at the entire first surface of the semiconductor body, the forming the doped region including:
forming one or more first sub-regions having a first doping density; and
forming one or more second sub-regions having a second doping density lower than the first doping density;
forming a body region, having a second conductivity opposite to the first conductivity, in the semiconductor body at the first surface;
forming a source region, having the first conductivity, in the body region at the first surface of the semiconductor body; and
forming a drain region, having the first conductivity, at the second surface.
2. The method of claim 1 , wherein forming the doped region further includes contacting the doped region with the body region.
3. The method of claim 1 , comprising:
forming a first gate structure on a respective first sub-region of the one or more first-sub regions;
forming an insulating portion covering the first gate structure;
forming the insulating portion overlapping the gate structure and overlapping the respective first sub-region of the one or more first-sub regions;
forming a first channel region within the semiconductor body, the first gate structure and the insulating portion overlapping the first channel region.
4. The method according to claim 3 , wherein forming the first gate structure includes:
forming a gate dielectric on the respective first sub-region of the one or more first sub-regions; and
forming a metal gate layer on the gate dielectric.
5. The method according to claim 3 , comprising forming a metal region over the insulating portion and over the semiconductor body.
6. The method according to claim 5 , wherein forming the metal region including forming the metal region to be electrically coupled with the source region and the body region at a contact zone.
7. The method according to claim 5 , comprising forming a second gate structure on a respective second sub-region of the one or more second-sub regions.
8. The method according to claim 7 , comprising forming a second channel region within the semiconductor body, the second gate structure overlapping the second channel region.
9. The method of claim 8 , wherein the first gate structure is spaced from the second gate structure at the first surface along a first direction, the first channel spaced from the second channel along the first direction.