Granted Patent B2

US 12,342,585 · App. 17/577,403 · Granted Jun 24, 2025

Inventors: Chia-Ling Wang (Yunlin County, TW); Ping-Hung Chiang (Hsinchu, TW); Wei-Lun Huang (Tainan, TW); Chia-Wen Lu (Chiayi County, TW); Ta-Wei Chiu (Changhua County, TW)

Assignee: UNITED MICROELECTRONICS CORP.

H10D62/115H10D84/0151H10D84/038

Abstract

Claims (12)

1. A semiconductor structure, comprising:

a substrate comprising a first device region and a second device region in proximity to the first device region, wherein the first device region is a medium-voltage device region and the second device region is a low-voltage device region;

a trench isolation structure in the substrate between the first device region and the second device region, wherein the trench isolation structure comprises a first bottom surface within the first device region and a second bottom surface within the second device region, wherein the first bottom surface is coplanar with the second bottom surface, wherein the trench isolation structure comprises a first top surface within the first device region and a second top surface within the second device region, wherein the first top surface is coplanar with the second top surface, wherein a top surface of the substrate within the first device region is lower than a top surface of the substrate within the second device region;

a first gate oxide layer on the top surface of the substrate within the first device region; and

a second gate oxide layer on the top surface of the substrate within the second device region, wherein the first gate oxide layer and the second gate oxide layer are in direct contact with the trench isolation structure.

2. The semiconductor structure according to claim 1 , wherein the trench isolation structure comprises a first top surface within the first device region and a second top surface within the second device region, wherein the first top surface is coplanar with the second top surface.

3. The semiconductor structure according to claim 1 ,

wherein the first gate oxide layer is thicker than the second gate oxide layer.

4. The semiconductor structure according to claim 3 further comprising:

a first gate disposed on the first gate oxide layer within the first device region; and

a second gate disposed on the second gate oxide layer within the second device region.

5. The semiconductor structure according to claim 4 , wherein the first gate and the second gate are metal gates.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (44)