Semiconductor structure and manufacturing method thereof
The present disclosure provides a semiconductor structure and a manufacturing method thereof. The manufacturing method of a semiconductor structure includes providing a substrate having trenches, regions other than the trenches in the substrate form a plurality of active regions at intervals; forming a first isolation layer and a second isolation layer, a top surface of the first isolation layer is lower than a top surface of the second isolation layer, a groove is formed between the second isolation layer and the active region; forming a barrier layer in the groove, an etching rate of the barrier layer is lower than an etching rate of the first isolation layer; and forming a third isolation layer in an intermediate trench, the intermediate trench is filled with the third isolation layer, and the first isolation layer, the second isolation layer, the third isolation layer, and the barrier layer form an isolation structure.
1. A manufacturing method of a semiconductor structure, comprising:
providing a substrate, wherein trenches are provided in the substrate, and regions other than the trenches in the substrate form a plurality of active regions at intervals;
forming a first isolation layer and a second isolation layer that are sequentially stacked on an inner wall of the trench, wherein a top surface of the first isolation layer is lower than a top surface of the second isolation layer, such that a groove is formed between the second isolation layer and the active region, and the second isolation layer defines an intermediate trench in the trench;
forming a barrier layer in the groove, wherein an etching rate of the barrier layer is lower than an etching rate of the first isolation layer; and
forming a third isolation layer in the intermediate trench, wherein the intermediate trench is filled with the third isolation layer, and the first isolation layer, the second isolation layer, the third isolation layer, and the barrier layer form an isolation structure;
wherein the forming a first isolation layer and a second isolation layer that are sequentially stacked on an inner wall of the trench comprises:
forming a first initial isolation layer on the inner wall of the trench, wherein the first initial isolation layer covers a top surface of the substrate;
forming a second initial isolation layer on the first initial isolation layer; and
removing the first initial isolation layer located on the top surface of the substrate and a part of the first initial isolation layer that is located on a sidewall of the trench, and removing the second initial isolation layer located on the top surface of the substrate, wherein the retained first initial isolation layer forms the first isolation layer, and the retained second initial isolation layer forms the second isolation layer; and
wherein the removing the first initial isolation layer located on the top surface of the substrate and a part of the first initial isolation layer that is located on a sidewall of the trench, and removing the second initial isolation layer located on the top surface of the substrate further comprises:
removing the active region by a certain thickness, wherein a filling region is formed between the retained active region and the barrier layer.
2. The manufacturing method of a semiconductor structure according to claim 1 , wherein the barrier layer is further provided with an extension portion located between the second isolation layer and the third isolation layer.
3. The manufacturing method of a semiconductor structure according to claim 2 , wherein a material of the barrier layer comprises at least one of silicon carbide nitride, silicon carbon oxide, and silicon boron nitride.
4. The manufacturing method of a semiconductor structure according to claim 1 , wherein the groove has a depth of 60 nm to 80 nm.
5. The manufacturing method of a semiconductor structure according to claim 1 , wherein the forming a barrier layer in the groove comprises:
forming an initial barrier layer in the groove, wherein the initial barrier layer extends to an outside of the groove and covers a top surface of the active region and an inner wall of the second isolation layer; and
removing the initial barrier layer located on the top surface of the active region, wherein the initial barrier layer retained in the groove forms the barrier layer, and the initial barrier layer retained on the inner wall of the second isolation layer forms an extension portion of the barrier layer.
6. The manufacturing method of a semiconductor structure according to claim 5 , wherein the forming a third isolation layer in the intermediate trench comprises:
forming a third initial isolation layer in the intermediate trench, wherein the third initial isolation layer extends to an outside of the intermediate trench and covers the top surface of the second isolation layer and a top surface of the barrier layer as well as an interior of the filling region; and
planarizing the third initial isolation layer, such that the third initial isolation layer located in the intermediate trench forms the third isolation layer, the third initial isolation layer located in the filling region forms a gate oxide layer, and a top surface of the gate oxide layer is flush with the top surface of the barrier layer.
7. The manufacturing method of a semiconductor structure according to claim 6 , after the planarizing the third initial isolation layer, the manufacturing method further comprises:
forming a gate structure and an insulating layer that are sequentially stacked on the gate oxide layer.
8. A semiconductor structure, comprising:
a substrate, wherein trenches are provided in the substrate, and regions other than the trenches in the substrate form a plurality of active regions at intervals;
a first isolation layer, wherein the first isolation layer is provided on an inner wall of the trench;
a second isolation layer, wherein the second isolation layer is provided on the first isolation layer, and a top surface of the second isolation layer is higher than a top surface of the first isolation layer, such that the second isolation layer and the substrate define a groove;
a barrier layer, wherein the barrier layer is provided in the groove, and an etching rate of the barrier layer is lower than an etching rate of the first isolation layer; and
a third isolation layer, wherein the third isolation layer is provided on an inner wall of the second isolation layer, and a region defined by the second isolation layer is filled with the third isolation layer;
wherein the first isolation layer and the second isolation layer are formed by:
forming a first initial isolation layer on the inner wall of the trench, wherein the first initial isolation layer covers a top surface of the substrate;
forming a second initial isolation layer on the first initial isolation layer; and
removing the first initial isolation layer located on the top surface of the substrate and a part of the first initial isolation layer that is located on a sidewall of the trench, and removing the second initial isolation layer located on the top surface of the substrate, wherein the retained first initial isolation layer forms the first isolation layer, and the retained second initial isolation layer forms the second isolation layer; and
wherein the removing the first initial isolation layer located on the top surface of the substrate and a part of the first initial isolation layer that is located on a sidewall of the trench, and removing the second initial isolation layer located on the top surface of the substrate further comprises:
removing the active region by a certain thickness, wherein a filling region is formed between the retained active region and the barrier layer.
9. The semiconductor structure according to claim 8 , wherein a material of the barrier layer comprises at least one of silicon carbide nitride, silicon carbon oxide, and silicon boron nitride.
10. The semiconductor structure according to claim 8 , wherein the barrier layer comprises an extension portion located between the second isolation layer and the third isolation layer.
11. The semiconductor structure according to claim 10 , wherein a top surface of the barrier layer is higher than a top surface of the active region; and a gate oxide layer is provided in a region defined by the barrier layer and the active region.
12. The semiconductor structure according to claim 11 , the semiconductor structure further comprises a gate structure and an insulating layer, wherein the gate structure comprises a first conductive layer and a second conductive layer that are sequentially stacked, the first conductive layer is arranged on the gate oxide layer, and the insulating layer is arranged on the second conductive layer.
13. The semiconductor structure according to claim 8 , wherein a material of the first isolation layer and a material of the third isolation layer both comprise silicon oxide, and a material of the second isolation layer comprises silicon nitride.