Shallow trench isolation structures
Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.
1. A method of forming a semiconductor device, comprising:
forming a high-k gate dielectric layer on a semiconductor substrate comprising a first silicon layer, a second silicon layer, and a buried oxide layer disposed between the first silicon layer and the second silicon layer; and
forming a shallow trench isolation structure formed in the semiconductor substrate, wherein forming a shallow trench isolation structure comprises:
forming a shallow trench in the substrate through the first silicon layer, the buried oxide layer and partially through the second silicon layer;
forming a first liner conformally lining the shallow trench; and
filling the shallow trench with a trench fill material,
wherein the first liner is formed of a material having etch selectivity with regard to the trench fill material,
wherein forming the shallow trench isolation structure further comprises etching the first liner to recess the first liner down in the shallow trench and create a void region disposed between an upper recessed surface of the first liner and an upper surface of the first silicon layer, wherein the void region isolates the first liner from the high-k gate dielectric layer formed on the first silicon layer.
2. The method of claim 1 , wherein the first liner is a high-k dielectric liner.
3. The method of claim 1 , wherein forming the shallow trench isolation structure further comprises forming a second liner directly on exposed surfaces of the first and second silicon layers in the shallow trench, prior to forming the first liner.
4. The method of claim 1 , wherein the second liner is formed of oxynitride.
5. The method of claim 1 , wherein a thickness of the buried oxide layer is in a range of about 5 nm to about 75 nm.
6. The method of claim 1 , wherein the trench fill material comprises an oxide material.
7. A method of forming a semiconductor device, comprising:
forming a high-k gate dielectric layer on a semiconductor substrate comprising a first silicon layer, a second silicon layer, and a buried oxide layer disposed between the first silicon layer and the second silicon layer; and
forming a shallow trench isolation structure formed in the semiconductor substrate, wherein forming a shallow trench isolation structure comprises:
forming a shallow trench in the substrate through the first silicon layer, the buried oxide layer and partially through the second silicon layer;
forming a first liner conformally lining the shallow trench; and
filling the shallow trench with a trench fill material,
wherein the first liner is formed of a material having etch selectivity with regard to the trench fill material,
etching the first liner to recess the first liner down in the shallow trench and create a void region disposed between an upper recessed surface of the first liner and an upper surface of the first silicon layer; and
filling the void region with an insulating material, wherein the insulating material isolates the first liner from the high-k gate dielectric layer formed on the first silicon layer.
8. The method of claim 7 , wherein the first liner is a high-k dielectric liner.
9. The method of claim 7 , wherein forming the shallow trench isolation structure further comprises forming a second liner directly on exposed surfaces of the first and second silicon layers in the shallow trench, prior to forming the first liner.
10. The method of claim 9 , wherein the second liner is formed of oxynitride.
11. The method of claim 7 , wherein the insulating material is a material that does not conduct an appreciable amount of oxygen.
12. The method of claim 7 , wherein the insulating material comprises silicon nitride.
13. The method of claim 7 , wherein a thickness of the buried oxide layer is in a range of about 5 nm to about 75 nm.
14. The method of claim 7 , wherein the trench fill material comprises an oxide material.