Semiconductor memory device for performing program operation and method of operating the same
A semiconductor memory device may include a memory cell array circuit and a word line driving circuit. The memory cell array circuit may be connected with a plurality of word lines to store data in a program operation. The word line driving circuit may drive a selected word line among the word lines using a program voltage in the program operation. The word line driving circuit may drive each of non-selected word lines adjacent to the selected word line using a step pass voltage including at least two step voltages.
1. A semiconductor memory device comprising:
a memory cell array circuit including a plurality of word lines and a plurality of memory cells connected to each of the plurality of word lines; and
a word line driving circuit configured to apply a pulse of a program voltage to a selected word line of the plurality of the word lines in a program operation, to apply a pulse of a step pass voltage to at least one non-selected word line adjacent to the selected word line in the program operation, and to apply a pulse of a pass voltage to remaining non-selected word lines except for the at least one non-selected word line in the program operation,
wherein the at least one non-selected word line includes at least one first non-selected word line, and
the pulse of the step pass voltage applied to the at least one first non-selected word line is changed from a first voltage level higher than the pass voltage to a second voltage level lower than the first voltage level.
2. The semiconductor memory device of claim 1 , wherein the at least one non-selected word line further includes at least one second non-selected word line spaced apart from the selected word line by a second distance, and
the at least one first non-selected word line is spaced apart from the selected word line by a first distance greater than the second distance.
3. The semiconductor memory device of claim 2 , wherein the pulse of the step pass voltage applied to the at least one second non-selected word line is changed from a third voltage level to a fourth voltage level higher than the third voltage level.
4. The semiconductor memory device of claim 3 ,
wherein the third voltage level is lower than the pass voltage and the fourth voltage level is higher than the pass voltage.
5. The semiconductor memory device of claim 3 , wherein changing the pulse of the step pass voltage applied to the at least one first non-selected word line from the first voltage level to the second voltage level precedes changing the pulse of the step pass voltage applied to the at least one second non-selected word line from the third voltage level to the fourth voltage level.
6. The semiconductor memory device of claim 1 , wherein the pulse of the program voltage comprises at least one step voltage.
7. The semiconductor memory device of claim 1 , wherein the second voltage level corresponds to the pass voltage.
8. A method of operating a semiconductor memory device, the semiconductor memory device comprising a selected word line, at least one first non-selected word line spaced apart from the selected word line by a first distance, at least one second non-selected word line spaced apart from the selected word line by a second distance less than the first distance, and remaining non-selected word lines, the method comprising:
driving the selected word line with a pulse of a program voltage and driving the remaining non-selected word lines with a pulse of a pass voltage;
changing a voltage level of the at least one first non-selected word line from a first voltage level higher than the pass voltage to a second voltage level lower than the first voltage level during the driving the selected word line with the pulse of the program voltage; and
changing a voltage level of the at least one second non-selected word line from a third voltage level lower than the pass voltage to a fourth voltage level higher than the third voltage level during the driving the selected word line with the pulse of the program voltage.
9. The method of claim 8 , wherein the at least one second non-selected word line is adjacent to the selected word line and the second distance is a minimum distance between word lines.
10. The method of claim 9 , wherein the at least one first non-selected word line is adjacent to the at least one second non-selected word line.
11. The method of claim 8 , wherein the pulse of the program voltage includes at least one step voltage.
12. The method of claim 8 , wherein the second voltage level corresponds to the pass voltage and the fourth voltage level is higher than the pass voltage.
13. The method of claim 8 , wherein the changing the voltage level of the at least one first non-selected word line and the changing the voltage level of the at least one second non-selected word line are sequentially performed.
14. The method of claim 8 , wherein the changing the voltage level of the at least one first non-selected word line is performed during a program period in which the program voltage rises.
15. The method of claim 8 , wherein the changing the voltage level of the at least one second non-selected word line is performed during a program period in which the program voltage is driven at a preset step voltage.
16. An operating method of a memory device including first to fourth rows of memory cells, the operating method comprising:
applying a pulse of a program voltage to the first row;
applying a pulse of a first sequence of first and second step voltages to the second row during the applying the pulse of the program voltage;
applying a pulse of a second sequence of third and fourth step voltages to the third row during the applying the pulse of the program voltage; and
applying a pulse of a pass voltage to the fourth row during the applying the pulse of the program voltage, wherein:
the second to fourth rows are arranged sequentially farther from the first row,
the first step voltage has a lower level than the pass voltage,
each of the second and third step voltages has a higher level than the pass voltage, and
the fourth step voltage has substantially the same level as the pass voltage.
17. The operating method of claim 16 , wherein the applying the first sequence includes changing the first step voltage to the second step voltage while a voltage level of the first row is stable at a level of the program voltage.
18. The operating method of claim 16 , wherein the applying the second sequence includes changing the third step voltage to the fourth step voltage while a voltage level of the first row is transitioning to a level of the program voltage.