IP Library Granted Patent US 12,346,601
Granted Patent B2
US 12,346,601 · App. 18/124,208 · Granted Jul 1, 2025

Firmware-controlled and table-based conditioning for flexible storage controller

Inventors: Priyanka Nilay Thakore (Mountain View, CA); Chen Xiu (Beijing, CN); Lyle E. Adams (San Jose, CA); Wanqiang Zhang (Beijing, CN)
Assignee: Beijing Tenafe Electronic Technology Co., Ltd.
G06F3/0659G06F3/0604G06F3/0607G06F3/0619G06F3/0634G06F3/0655G06F3/0679G06F9/4881
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,346,601
App. No.
18/124,208
Granted
Jul 1, 2025
Kind
B2
Abstract

A hardware-implemented, pre-sequence execution checker is used to receive a set of firmware instructions that includes a suspend command, an intervening command, and a resume command, wherein the suspend command and the resume command are associated with suspending and resuming a same command, respectively; access a configurable conditions table that includes whether the suspend command and the resume command are supported by a storage media device; access state information that includes whether said same command has completed; and determine whether to perform or skip the suspend command based at least in part on the configurable conditions table and the state information. If it is determined to perform the suspend command, the suspend command and the intervening command are output. If it is determined to skip the suspend command, the intervening command is output.

Claims (67)

1. A storage controller system that manages a NAND Flash memory device, comprising:

a configurable conditions table, wherein:

in the event the NAND Flash memory device is associated with a first manufacturer, the configurable conditions table is configured using a first set of values corresponding to the first manufacturer; and

in the event the NAND Flash memory device is associated with a second manufacturer, the configurable conditions table is configured using a second set of values corresponding to the second manufacturer;

state information;

a processor that is configured to:

receive a set of firmware instructions that includes a suspend command, an intervening command, and a resume command, wherein:

the suspend command and the resume command are associated with suspending and resuming a same command, respectively;

access the configurable conditions table, wherein the configurable conditions table includes suspend-related condition information;

access the state information, wherein the state information indicates whether said same command has completed; and

determine whether to perform or skip the suspend command based at least in part on the suspend-related condition information and the state information; and

an interface that is configured to:

in response to determining to perform the suspend command, output the suspend command and the intervening command; and

in response to determining to skip the suspend command, output the intervening command.

2. The storage controller system recited in claim 1 , wherein the storage controller system is implemented using one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

3. The storage controller system recited in claim 1 , wherein it is determined to perform the suspend command in response to determining:

the state information indicates the NAND Flash memory device is busy.

4. The storage controller system recited in claim 1 , wherein:

the suspend command and the resume command are associated with suspending and resuming a same erase command to the NAND Flash memory device.

5. The storage controller system recited in claim 1 , wherein:

the suspend command and the resume command are associated with suspending and resuming a same program command to the NAND Flash memory device.

6. The storage controller system recited in claim 1 , wherein:

the NAND Flash memory device has a plurality of die, including a first die;

the suspend command, the intervening command, and the resume command are intended for the first die; and

it is determined to perform the suspend command in response to determining:

the state information indicates the first die is busy when it is being determined whether to perform or skip the suspend command.

7. The storage controller system recited in claim 1 , wherein:

the state information includes a sent indication that indicates whether the suspend command was sent and a fail indication that indicates whether the suspend command failed;

the state information includes suspend-related state information and determining whether to perform or skip the resume command is based at least in part on the suspend-related state information; and

the interface is further configured to: in response to determining to perform the resume command, output the resume command.

8. The storage controller system recited in claim 1 , wherein:

the NAND Flash memory device has a plurality of die, including a first die;

the state information includes a sent indication for the first die that indicates whether the suspend command was sent to the first die and a fail indication for the first die that indicates whether the suspend command failed for the first die;

the state information includes suspend-related state information and determining whether to perform or skip the resume command is based at least in part on the suspend-related state information; and

the interface is further configured to: in response to determining to perform the resume command, output the resume command.

9. A method for managing a NAND Flash memory device, comprising:

using a processor to:

receive a set of firmware instructions that includes a suspend command, an intervening command, and a resume command, wherein the suspend command and the resume command are associated with suspending and resuming a same command, respectively;

access a configurable conditions table, wherein:

in the event the NAND Flash memory device is associated with a first manufacturer, the configurable conditions table is configured using a first set of values corresponding to the first manufacturer;

in the event the NAND Flash memory device is associated with a second manufacturer, the configurable conditions table is configured using a second set of values corresponding to the second manufacturer; and

the configurable conditions table includes suspend-related condition information;

access a state information, wherein the state information indicates whether said same command has completed; and

determine whether to perform or skip the suspend command based at least in part on the suspend-related condition information and the state information;

in response to determining to perform the suspend command, outputting the suspend command and the intervening command; and

in response to determining to skip the suspend command, outputting the intervening command.

10. The method recited in claim 9 , wherein the method is performed using one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

11. The method recited in claim 9 , wherein it is determined to perform the suspend command in response to determining:

the state information indicates the NAND Flash memory device is busy.

12. The method recited in claim 9 , wherein:

the suspend command and the resume command are associated with suspending and resuming a same erase command to the NAND Flash memory device.

13. The method recited in claim 9 , wherein:

the suspend command and the resume command are associated with suspending and resuming a same program command to the NAND Flash memory device.

14. The method recited in claim 9 , wherein:

the NAND Flash memory device has a plurality of die, including a first die;

the suspend command, the intervening command, and the resume command are intended for the first die; and

it is determined to perform the suspend command in response to determining:

the state information indicates the first die is busy when it is being determined whether to perform or skip the suspend command.

15. The method recited in claim 9 , wherein:

the state information includes a sent indication that indicates whether the suspend command was sent and a fail indication that indicates whether the suspend command failed;

the state information includes suspend-related state information and determining whether to perform or skip the resume command is based at least in part on the suspend-related state information; and

the method further includes: in response to determining to perform the resume command, outputting the resume command.

16. The method recited in claim 9 , wherein:

the NAND Flash memory device has a plurality of die, including a first die;

the state information includes a sent indication for the first die that indicates whether the suspend command was sent to the first die and a fail indication for the first die that indicates whether the suspend command failed for the first die;

the state information includes suspend-related state information and determining whether to perform or skip the resume command is based at least in part on the suspend-related state information; and

the method further includes: in response to determining to perform the resume command, outputting the resume command.

Continuity (3)
Continuation 17866149 · Jul 15, 2022
Provisional Application 63226009 · Jul 27, 2021
Related Publication 20230221894A1 · Jul 13, 2023
References Cited (43)
US 5479616A · Garibay, Jr. · 1995 [cited by applicant]
US 6487716B1 · Choi · 2002 [cited by applicant]
US 8972627B2 · Strasser · 2015 [cited by applicant]
US 9455955B2 · Fetik · 2016 [cited by applicant]
US 9569116B1 · Colgrove · 2017 [cited by applicant]
US 10331370B2 · Fernandez · 2019 [cited by applicant]
US 20150363109A1 · Frick · 2015 [cited by applicant]
US 20160170768A1 · Alexander · 2016 [cited by applicant]
US 20190121720A1 · Jung · 2019 [cited by applicant]
US 20190286364A1 · Gavens · 2019 [cited by applicant]
US 20190310795A1 · Mathada · 2019 [cited by examiner]
US 20200117401A1 · Shibata · 2020 [cited by applicant]
US 20200410102A1 · Miller · 2020 [cited by applicant]
US 20210247937A1 · Angoth · 2021 [cited by examiner]
US 20220101927A1 · Madraswala · 2022 [cited by applicant]
US 20220147247A1 · Ammari · 2022 [cited by applicant]
US 20220189561A1 · Kamata · 2022 [cited by applicant]
US 20230143341A1 · Kim · 2023 [cited by examiner]
CN 1303043 · 2005 [cited by applicant]
CN 101236538 · 2010 [cited by applicant]
CN 102112966 · 2011 [cited by applicant]
CN 102301339 · 2011 [cited by applicant]
CN 103348330 · 2013 [cited by applicant]
CN 103562894 · 2014 [cited by applicant]
CN 105723317 · 2016 [cited by applicant]
CN 106469026 · 2017 [cited by applicant]
CN 107615249 · 2018 [cited by applicant]
CN 110476153 · 2019 [cited by applicant]
CN 110879789 · 2020 [cited by applicant]
CN 112506758 · 2021 [cited by applicant]
EP 3696679A1 · 2020 [cited by examiner]
JP 2015026230 · 2015 [cited by applicant]
TW 200715134 · 2007 [cited by applicant]
TW 200849015 · 2008 [cited by applicant]
TW 201111981 · 2011 [cited by applicant]
TW 201636844 · 2016 [cited by applicant]
TW 201810025 · 2018 [cited by applicant]
TW 202032359 · 2020 [cited by applicant]
TW 202032378 · 2020 [cited by applicant]
Intel, Intel StrataFlash Memory (J3), 2005, Intel, 256-Mbit (x8/x16) datasheet, pp. 1-72 https://docs.rs-online.com/6091/0900766b8062d526.pdf (Year: 2005). [cited by applicant]
Becht et al. “IBM z14: Advancing the I/O storage and networking channel adapter.” IBM Journal of Research and Development 62.2/3 (2018): 14-1. [cited by applicant]
Hu et al., Backdoor Detection in Embedded System Firmware Without File System, Journal on Communications, Aug. 2013. [cited by applicant]
Wu Zhengyang, Design of Image Processing Hardware Platform Based on DSP and FPGA, University of Electronic Science and Technology of China, 2016. [cited by applicant]