IP Library Granted Patent US 12,349,485
Granted Patent B2
US 12,349,485 · App. 18/625,946 · Granted Jul 1, 2025

Imaging device

Inventors: Masayuki Takase (Osaka, JP); Shunsuke Isono (Osaka, JP); Yuuko Tomekawa (Osaka, JP)
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
H10F39/803H10F39/811
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Quick Facts
Patent No.
US 12,349,485
App. No.
18/625,946
Granted
Jul 1, 2025
Kind
B2
Abstract

An electronic device includes: a capacitor; an insulating layer; at least one trench provided in the insulating layer; and a first conductive plug, at least part of which is surrounded by the insulating layer. The capacitor includes: a first lower electrode provided along an inner wall of the at least one trench, a dielectric layer provided on the first lower electrode, and an upper electrode provided on the dielectric layer. At least part of the first conductive plug is positioned between an upper surface of the insulating layer and a lowermost portion of the at least one trench.

Claims (38)

1. An imaging device comprising:

a semiconductor substrate;

a photoelectric converter that is embedded in the semiconductor substrate and that generates a signal charge by photoelectric conversion;

a first diffusion region that stores the signal charge transferred from the photoelectric converter;

a capacitor that stores the signal charge generated by the photoelectric converter;

a first contact that is connected to the first diffusion region; and

a first wiring layer that is located between the semiconductor substrate and the capacitor, the first wiring layer including first wiring that is connected to the first contact.

2. The imaging device according to claim 1 , further comprising:

an amplifying transistor that includes a gate and that outputs a signal corresponding to the signal charge in the first diffusion region; and

a second contact that is connected to the gate of the amplifying transistor and the first wiring.

3. The imaging device according to claim 1 , wherein

the first wiring layer is disposed between the capacitor and the photoelectric converter.

4. The imaging device according to claim 1 , wherein

the capacitor has a trench structure.

5. The imaging device according to claim 1 , further comprising:

a second wiring layer, wherein

no wiring layer is located between the first wiring layer and the semiconductor substrate.

6. The imaging device according to claim 5 , further comprising:

an amplifying transistor that includes a gate and that outputs a signal corresponding to the signal charge in the first diffusion region, wherein

the first wiring layer does not include the gate of the amplifying transistor.

7. The imaging device according to claim 1 , wherein

the imaging device is a back-illuminated CMOS image sensor.

8. The imaging device according to claim 7 , wherein

the capacitor overlaps at least a part of the photoelectric converter in a plan view.

9. The imaging device according to claim 1 , wherein

the imaging device is a surface-illuminated CMOS image sensor.

10. The imaging device according to claim 9 , wherein

the capacitor does not overlap the photoelectric converter in a plan view.

11. The imaging device according to claim 1 , wherein

the capacitor includes

a first electrode that is located along an inner wall of at least one recess,

a dielectric layer that is located on the first electrode, and

a second electrode that is located on the dielectric layer.

12. The imaging device according to claim 11 , wherein

the at least one recess includes a plurality of recesses, and

the first electrode is located along an inner wall of each of the plurality of recesses.

13. The imaging device according to claim 11 , wherein

the first wiring layer is located between the semiconductor substrate and a bottom of the at least one recess.

Priority Claims (1)
JP 2018-072409 · Apr 4, 2018 · national
Continuity (3)
Continuation 17028627 · Sep 22, 2020
Continuation PCTJP2018045241 · Dec 10, 2018
Related Publication 20240274626A1 · Aug 15, 2024
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