Contact structure for semiconductor device
A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a second ILD layer over the first ILD layer, forming a source/drain contact structure within the first ILD layer and the second ILD layer, and selectively removing a portion of the source/drain contact structure to form a concave top surface of the source/drain contact structure.
1. A method, comprising:
forming a transistor on a substrate, wherein the transistor comprises:
a fin structure on the substrate;
a source/drain (S/D) region over the fin structure; and
a gate structure adjacent to the S/D region;
forming a first dielectric layer over the fin structure;
forming an etch stop layer (ESL) on the first dielectric layer;
forming a second dielectric layer on the ESL;
forming a contact structure comprising a conductive material and in contact with the transistor, wherein the conductive material extends continuously through the first dielectric layer, the ESL, and the second dielectric layer; and
forming a concavely-curved surface on the contact structure.
2. The method of claim 1 , further comprising:
forming an additional ESL on the second dielectric layer; and
forming a third dielectric layer on the additional ESL.
3. The method of claim 1 , further comprising forming a metal interconnect in contact with the concavely-curved surface of the contact structure.
4. The method of claim 3 , wherein the forming the metal interconnect comprises forming a conductive line and a conductive via, and wherein:
the conductive via is in contact with the contact structure; and
a width of the conductive via is less than a width of the contact structure adjacent to the concavely-curved surface.
5. The method of claim 3 , further comprising:
forming an additional metal interconnect connected to the gate structure, wherein a top surface of the metal interconnect is coplanar with a top surface of the additional metal interconnect.
6. The method of claim 1 , wherein the forming the contact structure comprises:
forming an opening in the first dielectric layer, the ESL, and the second dielectric layer to expose the S/D region;
depositing a conductive liner in the opening; and
depositing a metal on the conductive liner to fill the opening.
7. The method of claim 1 , wherein the forming the concavely-curved surface on the contact structure comprises selectively removing a portion of the contact structure to form the concavely-curved surface.
8. The method of claim 7 , wherein the selectively removing the portion of the contact structure comprises:
treating the portion of the contact structure in an oxygen plasma; and
wet etching the oxygen plasma treated portion to form the concavely-curved surface.
9. The method of claim 8 , wherein the wet etching the oxygen plasma treated portion comprises using a solution of deionized water and ozone, dilute hydrofluoric acid, and carbonated deionized water.
10. A method, comprising:
forming a transistor on a substrate, wherein the transistor comprises:
a fin structure on the substrate; and
a source/drain (S/D) region on the fin structure;
forming a first dielectric layer over the S/D region;
forming a first etch stop layer (ESL) on the first dielectric layer;
forming a second dielectric layer on the first ESL;
forming a contact structure in contact with the transistor, wherein the contact structure comprises a conductive liner extending continuously within the first ESL and the first and second dielectric layers;
forming a second ESL on the second dielectric layer;
forming a third dielectric layer over the contact structure;
forming a fourth dielectric layer over the third dielectric layer; and
forming an interconnect structure in contact with the contact structure, wherein the interconnect structure extends through the third and fourth dielectric layers and form a curved interface with the contact structure.
11. The method of claim 10 , wherein the forming the interconnect structure comprises forming a conductive line and a conductive via, and wherein:
the conductive via is in contact with the contact structure; and
a width of the conductive via is less than a width of the contact structure.
12. The method of claim 10 , further comprising:
forming a gate structure adjacent to the S/D region; and
forming an additional interconnect structure connected to the gate structure, wherein a top surface of the interconnect structure is coplanar with a top surface of the additional interconnect structure.
13. The method of claim 10 , wherein the forming the contact structure comprises:
forming an opening in the first dielectric layer, the ESL, and the second dielectric layer to expose the S/D region;
depositing the conductive liner in the opening; and
depositing a metal on the conductive liner to fill the opening.
14. The method of claim 10 , further comprising selectively removing a portion of the contact structure to form a concavely-curved surface.
15. The method of claim 14 , wherein the selectively removing the portion of the contact structure comprises:
treating the portion of the contact structure in an oxygen plasma; and
wet etching the oxygen plasma treated portion to form the concavely-curved surface.
16. A method, comprising:
forming a transistor on a substrate, wherein the transistor comprises a fin structure, a source/drain (S/D) region, and a gate structure;
forming a first dielectric layer over the fin structure;
forming a second dielectric layer over the first dielectric layer and the gate structure;
forming a first conductive structure connected to the transistor, wherein the first conductive structure has a concave surface; and
forming a second conductive structure in contact with the concave surface of the first conductive structure, wherein the second conductive structure comprises a top surface having a first curvature and a bottom surface having a second curvature greater than the first curvature.
17. The method of claim 16 , further comprising:
forming a third dielectric layer on the second dielectric layer;
forming a first interconnect in contact with the top surface of the second conductive structure; and
forming a second interconnect connected to the gate structure, wherein:
the second interconnect extends through the second and third dielectric layers; and
top surfaces of the first interconnect, the third dielectric layer, and the second interconnect are coplanar.
18. The method of claim 17 , wherein the forming the first interconnect comprises forming a conductive line and a conductive via, and wherein:
the conductive via is in contact with the top surface of the second conductive structure; and
a width of the conductive via is less than a width of the second conductive structure adjacent to the top surface.
19. The method of claim 16 , wherein the forming the first conductive structure comprises selectively removing a portion of the first conductive structure to form the concave surface.
20. The method of claim 16 , further comprising:
forming an etch stop layer (ESL) on the first dielectric layer, wherein the second conductive structure extends through the ESL; and
forming spacers positioned within the second dielectric layer along sidewalls of the second conductive structure.