Self-aligned source/drain metal contact
The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor fin over a substrate, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, first and second dielectric layers over the substrate, and an S/D contact disposed on the epitaxial S/D feature. The first and second dielectric layers have different material compositions. A first sidewall of the epitaxial S/D feature is facing the first dielectric layer, a second sidewall of the epitaxial S/D feature is facing the second dielectric layer, and the S/D contact partially covers a top surface of the epitaxial S/D feature and extends continuously to cover the first sidewall of the epitaxial S/D feature.
1. A semiconductor device, comprising:
a semiconductor fin over a substrate;
an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, wherein the epitaxial S/D feature includes a top surface, a first sidewall, and a second sidewall opposing the first sidewall;
a dielectric layer and a dielectric fin over the substrate, wherein each of the dielectric layer and the dielectric fin has a respective topmost portion below the top surface of the epitaxial S/D feature, wherein the first sidewall of the epitaxial S/D feature is facing the dielectric layer and the second sidewall of the epitaxial S/D feature is facing the dielectric fin, and wherein the dielectric layer and the dielectric fin have different material compositions; and
an S/D contact disposed on the epitaxial S/D feature, wherein the S/D contact partially covers the top surface of the epitaxial S/D feature and extends continuously to cover the first sidewall of the epitaxial S/D feature, and wherein the S/D contact is in contact with the dielectric layer and free of contact with the dielectric fin.
2. The semiconductor device of claim 1 , wherein the topmost portion of the dielectric layer is lower than the topmost portion of the dielectric fin.
3. The semiconductor device of claim 1 , wherein the S/D contact fully covers a top surface of the dielectric layer.
4. The semiconductor device of claim 1 , wherein the dielectric layer includes silicon and the dielectric fin includes a metal oxide.
5. The semiconductor device of claim 1 , wherein the semiconductor fin includes a first sidewall facing the dielectric layer and a second sidewall facing the dielectric fin, wherein the S/D contact intersects the top surface of the epitaxial S/D feature at a landing point, and wherein the landing point is laterally between the first and second sidewalls of the semiconductor fin.
6. The semiconductor device of claim 1 , wherein the semiconductor fin includes a first sidewall facing the dielectric layer and a second sidewall facing the dielectric fin, wherein the S/D contact intersects the top surface of the epitaxial S/D feature at a landing point, and wherein the landing point is laterally between the second sidewall of the semiconductor fin and the second sidewall of the epitaxial S/D feature.
7. The semiconductor device of claim 1 , wherein the dielectric layer is a first dielectric layer, the semiconductor device further comprising:
a second dielectric layer, the first dielectric layer and the semiconductor fin sandwiching the second dielectric layer, wherein the first and second dielectric layers have different material compositions.
8. The semiconductor device of claim 7 , wherein a top surface of the first dielectric layer is lower than a top surface of the second dielectric layer.
9. The semiconductor device of claim 7 , wherein a top surface of the first dielectric layer is higher than a top surface of the second dielectric layer.
10. The semiconductor device of claim 1 , wherein the semiconductor fin is a first semiconductor fin and the epitaxial S/D feature is a first epitaxial S/D feature, the semiconductor device further comprising:
a second semiconductor fin; and
a second epitaxial S/D feature disposed over the second semiconductor fin, wherein the first and second epitaxial S/D features sandwich the dielectric fin.
11. A semiconductor device, comprising:
a fin protruding from a substrate;
a dielectric layer and a dielectric fin over the substrate and sandwiching the fin, wherein the dielectric layer is lower than the dielectric fin;
an epitaxial feature disposed over the fin and between the dielectric layer and the dielectric fin;
an air gap stacked between the epitaxial feature and the dielectric fin; and
a conductive feature disposed over the epitaxial feature, wherein the conductive feature is in contact with a top surface of the epitaxial feature, a sidewall of the epitaxial feature that is facing the dielectric layer, and the dielectric layer, wherein the conductive feature is spaced apart from the dielectric fin, and wherein the top surface of the epitaxial feature is above topmost portions of both the dielectric layer and the dielectric fin.
12. The semiconductor device of claim 11 , wherein the conductive feature is free of contact with another sidewall of the epitaxial feature that is facing the dielectric fin.
13. The semiconductor device of claim 11 , further comprising:
a gate structure engaging the fin; and
a gate spacer disposed on sidewalls of the gate structure, wherein a portion of the gate spacer is disposed between the dielectric layer and the epitaxial feature.
14. The semiconductor device of claim 13 , wherein the conductive feature is in contact with the portion of the gate spacer.
15. The semiconductor device of claim 11 , wherein the epitaxial feature is in contact with the dielectric fin, and wherein the conductive feature separates the epitaxial feature from contacting the dielectric layer.
16. The semiconductor device of claim 11 , wherein the fin is a first fin and the epitaxial feature is a first epitaxial feature, the semiconductor device further comprising:
a second fin; and
a second epitaxial feature disposed over the second fin, wherein the dielectric fin is sandwiched between and in contact with the first and second epitaxial features.
17. The semiconductor device of claim 11 , wherein the air gap exposes a sidewall of the dielectric fin.
18. A semiconductor device, comprising:
a plurality of channel layers suspended over a substrate;
an epitaxial feature abutting the plurality of channel layers;
a first dielectric layer over the substrate and facing a first sidewall of the epitaxial feature;
a second dielectric layer over the substrate and facing a second sidewall of the epitaxial feature, wherein a top surface of the first dielectric layer is below a top surface of the second dielectric layer, and wherein each of the top surface of the first dielectric layer and the top surface of the second dielectric layer is below a topmost portion of the epitaxial feature; and
a conductive feature disposed over the epitaxial feature and in contact with the first sidewall of the epitaxial feature, wherein the conductive feature is free of contact with the second sidewall of the epitaxial feature.
19. The semiconductor device of claim 18 , wherein the conductive feature is in contact with the top surface of the first dielectric layer but free of contact with the top surface of the second dielectric layer.
20. The semiconductor device of claim 18 , wherein the first and second dielectric layers include different material compositions.