In-line device electrical property estimating method and test structure of the same
View Patent ↗A method for estimating at least one electrical property of a semiconductor device is provided. The method includes forming the semiconductor device and at least one testing unit on a substrate, irradiating the testing unit with at least one electron beam, estimating electrons from the testing unit induced by the electron beam, and estimating the electrical property of the semiconductor device according to intensity of the estimated electrons from the testing unit.
1. A semiconductor structure, comprising:
a device active region in a die area of a substrate, wherein the device active region comprises a device drain region;
a first test active region comprising a first test drain region;
a second test active region comprising a second test drain region;
a third test active region comprising a third test drain region;
a fourth test active region comprising a fourth test drain region, wherein:
the first test active region, the second test active region, the third test active region, and the fourth test active region are external to the die area of the substrate,
the first test active region is adjacent to the second test active region in a first direction,
the third test active region is adjacent to the first test active region in a second direction not parallel to the first direction,
the fourth test active region is adjacent to the first test active region in a third direction not parallel to the first direction and not parallel to the second direction,
the first test drain region and the second test drain region are different in area,
the first test drain region and the third test drain region are equal in area, and
the second test drain region and the fourth test drain region are equal in area;
a device gate region on the device active region;
a first test gate region on the first test active region; and
a second test gate region on the third test active region, wherein:
the first test gate region and the second test gate region are different in area,
the first test gate region comprises a body portion and a pad portion having a different width than a width of the body portion of the first test gate region, and
the second test gate region comprises a body portion and a pad portion having a different width than a width of the body portion of the second test gate region.
2. The semiconductor structure of claim 1 , comprising:
a fifth test active region external to the die area of the substrate and comprising a fifth test drain region, wherein the first test drain region, the second test drain region, and the fifth test drain region are arranged in a line.
3. The semiconductor structure of claim 2 , wherein:
the second test drain region is between the first test drain region and the fifth test drain region, and
the second test drain region is larger in area than the first test drain region and smaller in area than the fifth test drain region.
4. The semiconductor structure of claim 1 , wherein:
the first test active region comprises a first test source region,
the second test active region comprises a second test source region, and
the first test source region and the second test source region are equal in area.
5. The semiconductor structure of claim 1 , wherein:
the first test active region comprises a first test source region,
the second test active region comprises a second test source region,
a first area difference between the first test source region and the first test drain region is larger than a second area difference between the second test source region and the second test drain region.
6. The semiconductor structure of claim 1 , comprising:
a third test gate region on the second test active region, wherein the first test gate region and the third test gate region are equal in area.
7. The semiconductor structure of claim 1 , wherein the first test active region and the second test active region are in a scribe region of the substrate.
8. The semiconductor structure of claim 1 , wherein the pad portion of the first test gate region is adjacent to the body portion of the first test gate region when moving in the second direction.
9. The semiconductor structure of claim 1 , wherein:
the width of the pad portion of the first test gate region and the width of the body portion of the first test gate region are measured in the first direction, and
the width of the pad portion of the second test gate region and the width of the body portion of the second test gate region are measured in the first direction.
10. The semiconductor structure of claim 1 , comprising:
a fifth test active region external to the die area of the substrate, wherein:
the fifth test active region is adjacent to the second test active region in the first direction,
the first test active region and the third test active region are equal in area,
the first test active region and the second test active region are different in area,
the fifth test active region and the second test active region are different in area, and
the fifth test active region and the first test active region are different in area;
a third test gate region on the second test active region; and
a fourth test gate region on the fifth test active region, wherein:
the first test gate region and the third test gate region are equal in area, and
the fourth test gate region and the third test gate region are equal in area.
11. The semiconductor structure of claim 1 , comprising a third test gate region on the fourth test active region, wherein the second test gate region and the third test gate region are equal in area.
12. A semiconductor structure, comprising:
a device active region in a die area of a substrate;
a first test active region;
a second test active region;
a third test active region;
a fourth test active region; and
a fifth test active region, wherein:
the first test active region, the second test active region, the third test active region, the fourth test active region, and the fifth test active region are in a scribe region of the substrate,
the first test active region is adjacent to the second test active region in a first direction,
the third test active region is adjacent to the first test active region in a second direction not parallel to the first direction,
the fifth test active region is adjacent to the first test active region in a third direction not parallel to the first direction and not parallel to the second direction,
the fourth test active region is adjacent to the second test active region in the first direction,
the first test active region and the third test active region are equal in area,
the first test active region and the second test active region are different in area,
the fourth test active region and the second test active region are different in area, and
the fourth test active region and the first test active region are different in area;
a first test gate region crossing the first test active region;
a second test gate region crossing the second test active region;
a third test gate region crossing the third test active region;
a fourth test gate region crossing the fourth test active region; and
a fifth test gate region crossing the fifth test active region, wherein:
the first test gate region and the third test gate region are different in area,
the first test gate region and the second test gate region are equal in area,
the fourth test gate region and the second test gate region are equal in area, and
the fifth test gate region and the third test gate region are equal in area.
13. The semiconductor structure of claim 12 , wherein the first test gate region comprises a body portion and a pad portion.
14. The semiconductor structure of claim 13 , wherein the pad portion of the first test gate region has a different width than a width of the body portion of the first test gate region.
15. The semiconductor structure of claim 13 , wherein:
the third test gate region comprises a body portion and a pad portion, and
the pad portion of the first test gate region and the pad portion of the third test gate region are different in area.
16. A semiconductor structure, comprising:
a device active region in a die area of a substrate, wherein the device active region comprises a device drain region;
a first test active region comprising a first test drain region;
a second test active region comprising a second test drain region;
a third test active region comprising a third test drain region;
a fourth test active region comprising a fourth test drain region, wherein:
the first test active region, the second test active region, the third test active region, and the fourth test active region are external to the die area of the substrate,
the first test active region is adjacent to the second test active region in a first direction,
the third test active region is adjacent to the first test active region in a second direction not parallel to the first direction,
the fourth test active region is adjacent to the first test active region in a third direction not parallel to the first direction and not parallel to the second direction,
the first test drain region is smaller in area than the second test drain region,
the first test drain region and the third test drain region are equal in area, and
the second test drain region and the fourth test drain region are equal in area;
a device gate region on the device active region;
a first test gate region on the first test active region; and
a second test gate region on the third test active region, wherein:
the first test gate region and the second test gate region are different in area,
the first test gate region comprises a body portion and a pad portion having a different width than a width of the body portion of the first test gate region, and
the second test gate region comprises a body portion and a pad portion having a different width than a width of the body portion of the second test gate region.
17. The semiconductor structure of claim 16 , comprising:
a fifth test active region external to the die area of the substrate and comprising a fifth test drain region, wherein the first test drain region, the second test drain region, and the fifth test drain region are arranged in a line.
18. The semiconductor structure of claim 17 , wherein:
the second test drain region is between the first test drain region and the fifth test drain region, and
the second test drain region is formed to be smaller in area than the fifth test drain region.
19. The semiconductor structure of claim 16 , wherein:
the first test active region comprises a first test source region,
the second test active region comprises a second test source region, and
the first test source region and the second test source region are equal in area.
20. The semiconductor structure of claim 16 , wherein:
the first test active region comprises a first test source region,
the second test active region comprises a second test source region, and
a first area difference between the first test source region and the first test drain region is larger than a second area difference between the second test source region and the second test drain region.