Gate-all-around devices with optimized gate spacers and gate end dielectric
View Patent ↗A method includes providing a substrate, an isolation structure, a semiconductor fin having a stack of first and second semiconductor layers, a dummy gate, and outer spacers on opposing sidewalls of the dummy gate; etching the semiconductor fin to form source/drain (S/D) trenches; etching the second semiconductor layers from the S/D trenches to form gaps vertically between the first semiconductor layers; forming inner spacers in the gaps; epitaxially growing S/D features in the S/D trenches; forming an inter-layer dielectric layer over the S/D features; etching the dummy gate and the outer spacers to form a gate-end trench away from the semiconductor fin and over the isolation structure; and forming a gate-end dielectric feature filling the gate-end trench, wherein a dielectric constant of the gate-end dielectric feature is higher than both a dielectric constant of the outer spacers and a dielectric constant of the inner spacers.
1. A method, comprising:
providing a structure having a substrate, an isolation structure over the substrate, a semiconductor fin extending from the substrate and adjacent to the isolation structure, a first dielectric fin and a second dielectric fin adjacent to two opposing sides of the semiconductor fin, a dummy gate over the isolation structure and engaging a channel region of the semiconductor fin, and outer spacers on two opposing sidewalls of the dummy gate, wherein the semiconductor fin includes a stack of first semiconductor layers and second semiconductor layers alternatingly stacked, and wherein a height of the first dielectric fin is less than a height of the second dielectric fin;
etching the semiconductor fin proximate the two opposing sidewalls of the dummy gate to form two source/drain (S/D) trenches;
etching the second semiconductor layers from the S/D trenches to form gaps vertically between the first semiconductor layers;
forming inner spacers in the gaps;
epitaxially growing S/D features in the S/D trenches;
forming an inter-layer dielectric (ILD) layer over the S/D features, the dummy gate, and the outer spacers;
etching the dummy gate and the outer spacers to form a gate-end trench that is away from the semiconductor fin and over the isolation structure, the gate-end trench exposing the first dielectric fin; and
forming a gate-end dielectric feature filling the gate-end trench, wherein a dielectric constant of the gate-end dielectric feature is higher than both a dielectric constant of the outer spacers and a dielectric constant of the inner spacers.
2. The method of claim 1 , wherein the first dielectric fin extends into the isolation structure and oriented lengthwise parallel to the semiconductor fin.
3. The method of claim 1 , wherein portions of the outer spacers remain in the gate-end trench from a top view.
4. The method of claim 1 , wherein the gate-end dielectric feature includes a material whose dielectric constant is greater than 3.9.
5. The method of claim 1 , further comprising:
removing remaining portions of the dummy gate after the forming of the gate-end dielectric feature, thereby forming a gate trench;
removing the second semiconductor layers from the gate trench, leaving the first semiconductor layers suspended over the substrate and connected between the S/D features; and
forming a high-k metal gate in the gate trench, wherein portions of the high-k metal gate wrap around each of the first semiconductor layers.
6. The method of claim 5 , wherein the gate-end dielectric feature directly contacts the high-k metal gate.
7. The method of claim 5 , wherein the first dielectric fin directly contacts a lower portion of the high-k metal gate.
8. The method of claim 7 , wherein a top surface of the first dielectric fin is below a bottom surface of a topmost layer of the first semiconductor layers.
9. The method of claim 1 , wherein the etching of the dummy gate and the outer spacers completely etches the dummy gate and partially etches the outer spacers, wherein the forming of the gate-end dielectric feature includes forming a portion of the gate-end dielectric feature directly on a portion of the outer spacers.
10. A method, comprising:
providing a structure having a substrate, an isolation structure over the substrate, a semiconductor fin protruding from the substrate and higher than the isolation structure, a dummy gate over the isolation structure and engaging a channel region of the semiconductor fin, outer spacers on two opposing sidewalls of the dummy gate, and a dielectric fin over the isolation structure and oriented lengthwise parallel to the semiconductor fin, wherein the semiconductor fin includes a stack of first semiconductor layers and second semiconductor layers alternatingly stacked, and a top surface of the dielectric fin is below a bottom surface of a topmost layer of the first semiconductor layers;
etching the semiconductor fin proximate the two opposing sidewalls of the dummy gate to form two source/drain (S/D) trenches;
etching the second semiconductor layers from the S/D trenches to form gaps vertically between the first semiconductor layers;
forming inner spacers in the gaps;
epitaxially growing S/D features in the S/D trenches;
etching the dummy gate and the outer spacers to form a gate-end trench that is away from the semiconductor fin; and
filling a first dielectric material into the gate-end trench, wherein the first dielectric material, the outer spacers, and the inner spacers include different materials, and a dielectric constant of the first dielectric material is higher than both a dielectric constant of the outer spacers and a dielectric constant of the inner spacers.
11. The method of claim 10 , wherein the gate-end trench exposes a portion of the dielectric fin.
12. The method of claim 11 , wherein a portion of the first dielectric material is disposed directly on the portion of the dielectric fin.
13. The method of claim 12 , wherein the portion of the first dielectric material is sandwiched on two sides by the outer spacers.
14. The method of claim 10 , further comprising:
performing a chemical mechanical planarization process to the first dielectric material after the filling of the gate-end trench with the first dielectric material; and
replacing remaining portions of the dummy gate with high-k metal gates.
15. A method, comprising:
receiving an intermediate structure comprising a fin-shaped structure over a substrate, an isolation feature adjacent to a lower portion of the fin-shaped structure, and a first dielectric fin and a second dielectric fin adjacent to two opposing sides of an upper portion of the fin-shaped structure, the fin-shaped structure comprising a stack of alternating channel layers and sacrificial layers, and a height of the second dielectric fin being greater than a height of the first dielectric fin;
forming a dummy gate structure over a channel region of the fin-shaped structure;
forming a gate spacer extending along a sidewall surface of the dummy gate structure;
recessing portions of the fin-shaped structure not covered by the dummy gate structure to form source/drain recesses exposing sidewall surfaces of the channel region;
selectively recessing the sacrificial layers to form inner spacer recesses;
forming inner spacer features in the inner spacer recesses;
forming source/drain features in the source/drain recesses;
forming a dielectric feature extending into the dummy gate structure and disposed adjacent to the channel region of the fin-shaped structure, wherein the dielectric feature is disposed over and in direct contact with the first dielectric fin, and wherein a dielectric constant of the dielectric feature is greater than a dielectric constant of the gate spacer and a dielectric constant of the inner spacer features, and a top surface of the dielectric feature is no lower than a top surface of the dummy gate structure;
selectively removing the dummy gate structure and the sacrificial layers without substantially etching the dielectric feature to form gate trenches; and
forming a functional gate structure in the gate trenches, wherein the functional gate structure extends over the second dielectric fin.
16. The method of claim 15 , wherein the first dielectric fin is oriented lengthwise parallel to the fin-shaped structure.
17. The method of claim 15 , wherein a top surface of the functional gate structure is below a top surface of the dielectric feature.
18. The method of claim 15 , wherein a bottom surface of the dielectric feature is above a top surface of the isolation feature.
19. The method of claim 15 , wherein the fin-shaped structure is a first fin-shaped structure, the source/drain features are first source/drain features and comprise dopants having a first doping polarity, and the method further comprises:
forming a second fin-shaped structure over the substrate and adjacent to the first fin-shaped structure; and
forming second source/drain features coupled to channel layers of the second fin-shaped structure, the second source/drain features comprising dopants having a second doping polarity different than the first doping polarity,
wherein the functional gate structure extends over and wraps around channel layers of the first fin-shaped structure and channel layers of the second fin-shaped structures.
20. The method of claim 15 , further comprising:
forming a source/drain contact over and electrically coupled to one of the source/drain features,
wherein, in a cross-sectional view, the source/drain contact is in direct contact with the dielectric feature and the first dielectric fin.