Semiconductor device and manufacturing method thereof
A method for manufacturing a semiconductor device is provided. The method includes forming a first transistor over a substrate, wherein the first transistor comprises a first source/drain feature; depositing an interlayer dielectric layer around the first transistor; etching an opening in the interlayer dielectric layer to expose the first source/drain feature; conformably depositing a semimetal layer over the interlayer dielectric layer, wherein the semimetal layer has a first portion in the opening in the interlayer dielectric layer and a second portion over a top surface of the interlayer dielectric layer; and forming a source/drain contact in the opening in the interlayer dielectric layer.
1. A method for manufacturing a semiconductor device, comprising:
forming a first transistor over a substrate, wherein the first transistor comprises a first source/drain feature;
depositing an interlayer dielectric layer around the first transistor;
etching an opening in the interlayer dielectric layer to expose the first source/drain feature;
conformably depositing a semimetal layer over the interlayer dielectric layer, wherein the semimetal layer has a first portion in the opening in the interlayer dielectric layer and a second portion over a top surface of the interlayer dielectric layer;
forming a silicide region over the semimetal layer, wherein the silicide region comprises a semimetal material of the semimetal layer and a semiconductor material of the first source/drain feature; and
after forming the silicide region, forming a source/drain contact in the opening in the interlayer dielectric layer.
2. The method of claim 1 , wherein forming the source/drain contact comprises:
filling the opening with a conductive material; and
removing the second portion of the semimetal layer and a portion of the conductive material from a top surface of the interlayer dielectric layer.
3. The method of claim 1 , wherein forming the silicide region comprises:
depositing a metal-containing layer over the semimetal layer; and
annealing the metal-containing layer to form the silicide region by reacting with the semimetal layer and the first source/drain feature.
4. The method of claim 1 , wherein forming the source/drain contact is performed such that the source/drain contact is in direct contact with the semimetal layer.
5. The method of claim 1 , wherein the semimetal layer comprises Sb, Bi, or graphene.
6. The method of claim 1 , further comprising:
forming a spacer on a sidewall of the opening in the interlayer dielectric layer prior to conformably depositing the semimetal layer, wherein forming the source/drain contact is performed such that the source/drain contact is in contact with the spacer.
7. The method of claim 1 , wherein the first source/drain feature of the first transistor is an n-type source/drain feature.
8. The method of claim 1 , further comprising:
forming a second transistor over the substrate, wherein the second transistor comprises a second source/drain feature, wherein a dopant of the second source/drain feature is different from a dopant of the first source/drain feature; and
forming a patterned mask covering the second transistor, wherein selectively depositing the semimetal layer is performed when the second transistor is covered by the patterned mask.
9. A method for manufacturing a semiconductor device, comprising:
forming a first transistor over a substrate, wherein the first transistor comprises a first source/drain feature;
depositing an interlayer dielectric layer around the first transistor;
etching an opening in the interlayer dielectric layer to expose a top surface of the first source/drain feature;
forming a dielectric spacer in the opening in the interlayer dielectric layer;
selectively depositing a semimetal layer over the exposed top surface of the first source/drain feature and not over a top surface of the interlayer dielectric layer, wherein selectively depositing the semimetal layer is performed such that a topmost portion of the semimetal layer is lower than a top end of the dielectric spacer; and
forming a source/drain contact in the opening in the interlayer dielectric layer.
10. The method of claim 9 , further comprising:
forming a silicide region over the semimetal layer prior to forming the source/drain contact, wherein the silicide region comprises a semimetal material of the semimetal layer and a semiconductor material of the first source/drain feature.
11. The method of claim 9 , wherein forming the source/drain contact is performed such that the source/drain contact is in contact with the semimetal layer.
12. The method of claim 9 , further comprising:
forming a second transistor over the substrate, wherein the second transistor comprises a second source/drain feature; and
forming a patterned mask covering the second transistor, wherein selectively depositing the semimetal layer is performed when the second transistor is covered by the patterned mask.
13. The method of claim 12 , wherein the first source/drain feature is an n-type source/drain feature, and the second source/drain feature is a p-type source/drain feature.
14. A semiconductor device, comprising:
a semiconductor substrate;
a first transistor over the semiconductor substrate, wherein the first transistor comprises a first gate structure and a first source/drain epitaxial feature adjacent the first gate structure;
a semimetal layer over the first source/drain epitaxial feature;
a first source/drain contact over the semimetal layer;
a second transistor over the semiconductor substrate, wherein the second transistor comprises a second gate structure and a second source/drain epitaxial feature adjacent the second gate structure; and
a second source/drain contact over the second source/drain epitaxial feature, wherein the second source/drain contact and the second source/drain epitaxial feature have no material of the semimetal layer therebetween.
15. The semiconductor device of claim 14 , further comprising:
a silicide region between the semimetal layer and the first source/drain contact.
16. The semiconductor device of claim 14 , wherein the first source/drain epitaxial feature is an n-type source/drain epitaxial feature, and the second source/drain epitaxial feature is a p-type source/drain epitaxial feature.
17. The semiconductor device of claim 14 , wherein the semimetal layer comprises Sb, Bi, or graphene.
18. The semiconductor device of claim 15 , wherein the silicide region comprises a semimetal material of the semimetal layer and a semiconductor material of the first source/drain contact.
19. The semiconductor device of claim 14 , wherein the semimetal layer surrounds the first source/drain contact.
20. The semiconductor device of claim 14 , wherein a top surface of the semimetal layer is lower than a top surface of the first source/drain contact.