Semiconductor memory with different threshold voltages of memory cells
According to one embodiment, a semiconductor memory includes a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells. Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.
1. A semiconductor memory comprising:
first to N-th memory cells, N being an integer of 3 or more;
first to N-th bit lines connected to the first to N-th memory cells, respectively;
first to N-th latch circuits connected to the N-th bit lines; and
a controller, wherein
each of threshold voltages of the first to N-th memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, a third threshold voltage higher than the second threshold voltage, and a fourth threshold voltage higher than the third threshold voltage,
data of six or more bits including a first bit, a second bit, a third bit, a fourth bit, a fifth bit, and a sixth bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell, based on a data allocation,
the controller is configured to perform a read operation for one bit data based on the first to N-th memory cells, respectively,
the controller applies, to read the data of one of the first bit, the second bit, the third bit, the fourth bit, the fifth bit, or the sixth bit, one or more kinds of read voltages to gates of the first to N-th memory cells in the read operation to cause the first to N-th latch circuits to store first to N-th interim data, respectively, and output the read data depending on the data allocation, and
in the data allocation, a combination of the first to N-th memory cell commonly each set with the fourth threshold voltage does not overlap with another combination.
2. The memory of claim 1 , further comprising:
first to N-th word lines coupled to the first to N-th memory cells, respectively, wherein
upon reception of write data of six pages including the first bit, the second bit, the third bit, the fourth bit, the fifth bit, and the sixth bit, the controller performs a write operation to the first to N-th memory cells based on the six-page write data.
3. The memory of claim 2 , wherein
in a read operation to a first page including the first bit, the controller reads data from the first to N-th memory cells by applying one type of read voltage to each of the first to N-th word lines, determines read data of the first page based on first to N-th read data read from the first to N-th memory cells, respectively, and outputs the determined read data of the first page to an outside of the controller.
4. The memory of claim 1 , wherein
each of the threshold voltages is one of 64 combinations of possible threshold voltages.
5. The memory of claim 4 , wherein
different six-bit data is allocated to each of the 64 combinations of threshold voltages.
6. The memory of claim 2 , wherein
in a read operation of each of the first page, the second page, the third page, the fourth page, the fifth page, and the sixth page, respective combinations of three read voltages are applied.
7. The memory of claim 2 , wherein
in a write operation, a memory controller transmits a first command set, a second command set, a third command set, a fourth command set, a fifth command set, and a sixth command set, respectively for command for instructing operations to read respective of a first page, a second page, a third page, a fourth page, a fifth page, and a sixth page.
8. A semiconductor memory comprising:
a first memory cell;
a first bit line connected to the first memory cell;
a first latch circuit connected to the first bit line;
a second memory cell;
a second bit line connected to the second memory cell;
a second latch circuit connected to the second bit line; and
a controller, wherein
a threshold voltage of each of the first and second memory cells is set to any of at least three threshold voltage levels including a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage,
data of at least three bits including a first bit, a second bit and a third bit is stored using a combination of the threshold voltages of the first and second memory cells based on a data allocation,
the controller is configured to perform a read operation on the first and second memory cells for at least one bit data,
the controller, to read the data of one of the first bit, the second bit, or the third bit, applies at least one kind of read voltage to gate of the first and second memory cells in the read operation to cause the first and second latch circuits to store first and second interim data, respectively, and output the read data depending on the data allocation, and
in the data allocation, a combination of the first and second memory cells each set with the third threshold voltage does not overlap with another combination.
9. The memory of claim 8 , further comprising:
a word line coupled to the first and second memory cells.
10. The memory of claim 9 , further comprising:
a third memory cell, the threshold voltage which is set to any of the at least three threshold voltage levels.
11. The memory of claim 9 , wherein
the first and second memory cells are independently supplied with different read voltages.
12. A semiconductor memory comprising:
a first memory cell;
a first bit line connected to the first memory cell;
a first latch circuit connected to the first bit line;
a second memory cell;
a second bit line connected to the second memory cell;
a second latch circuit connected to the second bit line; and
a controller, wherein
a threshold voltage of each of the first and second memory cells is set to any of at least eight threshold voltage levels including a first threshold voltage, a second threshold voltage higher than the first threshold voltage, a third threshold voltage higher than the second threshold voltage, a fourth threshold voltage higher than the third threshold voltage, a fifth threshold voltage higher than the fourth threshold voltage, a sixth threshold voltage higher than the fifth threshold voltage, a seventh threshold voltage higher than the sixth threshold voltage, and an eighth threshold voltage higher than the seventh threshold voltage,
data of at least six bits including a first bit, a second bit, a third bit, a fourth bit, a fifth bit and a sixth bit is stored using a combination of the threshold voltages of the first and second memory cells, based on a data allocation,
the controller is configured to perform a read operation on the first and second memory cells for at least one bit data, and
the controller applies, to read the data of one of the first bit, the second bit, the third bit, the fourth bit, or the fifth bit, at least one kind of read voltage to gates of the first and second memory cells in the read operation to cause the first to N-th latch circuits to store first to N-th interim data, respectively, and output the read data depending on the data allocation, and
in the data allocation, a combination of the first and second memory cells each set with the third threshold voltage does not overlap with another combination.
13. The memory of claim 12 , further comprising:
a first word line coupled to the gate of the first memory cell; and
a second word line coupled to the gate of the second memory cell,
wherein
upon reception of write data of six pages including the first bit, the second bit, the third bit, the fourth bit, the fifth bit, and the sixth bit, the controller performs a write operation to the first and second memory cells based on the six-page write data.
14. The memory of claim 12 , wherein
each of the threshold voltages is one of 64 combinations of possible threshold voltages.
15. The memory of claim 14 , wherein
different six-bit data is allocated to each of the 64 combinations of threshold voltages.
16. The memory of claim 15 , wherein
in a write operation, a memory controller transmits a first command set, a second command set, a third command set, a fourth command set, a fifth command set, and a sixth command set, respectively for command for instructing operations to read respective of a first page, a second page, a third page, a fourth page, a fifth page, and a sixth page.