Varying-polarity read operations for polarity-written memory cells
Methods, systems, and devices for varying-polarity read operations for polarity-written memory cells are described. Memory cells may be programmed to store different logic values based on applying write voltages of different polarities to the memory cells. A memory device may read the logic values based on applying read voltages to the memory cells, and the polarity of the read voltages may vary such that at least some read voltages have one polarity and at least some read voltages have another polarity. The read voltage polarity may vary randomly or according to a pattern and may be controlled by the memory device or by a host device for the memory device.
1. A method, comprising:
storing, at a memory device, a plurality of logic values at a plurality of memory cells;
receiving one or more read commands;
applying, based at least in part on the one or more read commands, read pulses to the plurality of memory cells, wherein:
a first subset of the read pulses, each having a first polarity, is applied to a first subset of memory cells of the plurality of memory cells; and
a second subset of the read pulses, each having a second polarity, is applied to a second subset of memory cells of the plurality of memory cells;
inverting, based at least in part on the first polarity being different than a default polarity, a first subset of logic values sensed from the first subset of memory cells using the first subset of the read pulses; and
transmitting, based at least in part applying the read pulses, signaling that indicates the inverted first subset of logic values and a second subset of un-inverted logic values sensed from the second subset of memory cells using the second subset of the read pulses.
2. The method of claim 1 , wherein a read pulse of the first subset is applied after a first read pulse of the second subset and before a second read pulse of the second subset.
3. The method of claim 1 , wherein each of the one or more read commands is associated with an indication of whether a corresponding one or more of the read pulses has the first polarity or the second polarity.
4. The method of claim 1 , wherein, for each of the one or more read commands, whether a corresponding one or more of the read pulses has the first polarity or the second polarity is random.
5. The method of claim 1 , wherein, for each of the one or more read commands, whether a corresponding one or more of the read pulses has the first polarity or the second polarity is based at least in part on a pattern.
6. The method of claim 1 , further comprising:
applying a first subset of write pulses to a first subset of the plurality of memory cells, the first subset of write pulses having the first polarity for writing a first logic value; and
applying a second subset of write pulses to a second subset of the plurality of memory cells, the second subset of write pulses having the second polarity for writing a second logic value, wherein the plurality of logic values are stored at the plurality of memory cells based at least in part on applying the first subset of write pulses and the second subset of write pulses.
7. A memory system, comprising:
one or more memory devices; and
one or more controllers coupled with the one or more memory devices and configured to cause the memory system to:
store, at the one or more memory devices, a plurality of logic values at a plurality of memory cells;
receive one or more read commands;
apply, based at least in part on the one or more read commands, read pulses to the plurality of memory cells, wherein:
a first subset of the read pulses, each having a first polarity, is applied to a first subset of memory cells of the plurality of memory cells; and
a second subset of the read pulses, each having a second polarity, is applied to a second subset of memory cells of the plurality of memory cells;
invert, based at least in part on the first polarity being different than a default polarity, a first subset of logic values sensed from the first subset of memory cells using the first subset of the read pulses; and
transmit, based at least in part applying the read pulses, signaling that indicates the inverted first subset of logic values and a second subset of un-inverted logic values sensed from the second subset of memory cells using the second subset of the read pulses.
8. The memory system of claim 7 , wherein a read pulse of the first subset is applied after a first read pulse of the second subset and before a second read pulse of the second subset.
9. The memory system of claim 7 , wherein each of the one or more read commands is associated with an indication of whether a corresponding one or more of the read pulses has the first polarity or the second polarity.
10. The memory system of claim 7 , wherein, for each of the one or more read commands, whether a corresponding one or more of the read pulses has the first polarity or the second polarity is random.
11. The memory system of claim 7 , wherein, for each of the one or more read commands, whether a corresponding one or more of the read pulses has the first polarity or the second polarity is based at least in part on a pattern.
12. The memory system of claim 7 , wherein the one or more controllers is further configured to cause the memory system to:
apply a first subset of write pulses to a first subset of the plurality of memory cells, the first subset of write pulses having the first polarity for writing a first logic value; and
apply a second subset of write pulses to a second subset of the plurality of memory cells, the second subset of write pulses having the second polarity for writing a second logic value, wherein the plurality of logic values are stored at the plurality of memory cells based at least in part on applying the first subset of write pulses and the second subset of write pulses.
13. A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of an electronic device, cause the electronic device to:
store a plurality of logic values at a plurality of memory cells;
receive one or more read commands;
apply, based at least in part on the one or more read commands, read pulses to the plurality of memory cells, wherein:
a first subset of the read pulses, each having a first polarity, is applied to a first subset of memory cells of the plurality of memory cells; and
a second subset of the read pulses, each having a second polarity, is applied to a second subset of memory cells of the plurality of memory cells; and
transmit, based at least in part applying the read pulses, signaling that indicates a first subset of inverted logic values and a second subset of un-inverted logic values sensed from the second subset of memory cells using the second subset of the read pulses.
14. The non-transitory computer-readable medium of claim 13 , wherein a read pulse of the first subset is applied after a first read pulse of the second subset and before a second read pulse of the second subset.
15. The non-transitory computer-readable medium of claim 13 , wherein each of the one or more read commands is associated with an indication of whether a corresponding one or more of the read pulses has the first polarity or the second polarity.
16. The non-transitory computer-readable medium of claim 13 , wherein, for each of the one or more read commands, whether a corresponding one or more of the read pulses has the first polarity or the second polarity is random.
17. The non-transitory computer-readable medium of claim 13 , wherein, for each of the one or more read commands, whether a corresponding one or more of the read pulses has the first polarity or the second polarity is based at least in part on a pattern.