IP Library › Granted Patent US 12,374,882
Granted Patent B2
US 12,374,882 · App. 18/522,284 · Granted Jul 29, 2025

Integrated circuits with CDM ESD protection capabilities

Inventor: Chien Yu Chen (New Taipei, TW)
Assignee: NANYA TECHNOLOGY CORPORATION
H02H9/046
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Quick Facts
Patent No.
US 12,374,882
App. No.
18/522,284
Granted
Jul 29, 2025
Kind
B2
Abstract

An integrated circuit includes a power rail, a connecting pad, a first internal circuit, a second internal circuit, and an electrostatic discharge (ESD) protection circuit. The first internal circuit is coupled to the connecting pad through a first signal wire. The second internal circuit is coupled to the first internal circuit through a second signal wire. The ESD protection circuit is coupled between the second signal wire and the power rail. When charged-device model (CDM) ESD occurs in the integrated circuit, the ESD protection circuit conducts ESD charge on the second signal wire to the power rail.

Claims (31)

1. An integrated circuit, comprising:

a first power rail;

a connecting pad;

a first internal circuit coupled to the connecting pad through a first signal wire;

a second internal circuit coupled to the first internal circuit through a second signal wire; and

a first electrostatic discharge (ESD) protection circuit coupled between the second signal wire and the first power rail, wherein

in response to charged-device model ESD occurring in the integrated circuit, the first ESD protection circuit conducts ESD charge on the second signal wire to the first power rail.

2. The integrated circuit as claimed in claim 1 , wherein the first power rail is configured to transmit a power voltage or a reference voltage.

3. The integrated circuit as claimed in claim 1 , further comprising:

a second ESD protection circuit coupled between the second signal wire and a second power rail, wherein

the first power rail is configured to transmit one of a power voltage and a reference voltage, and the second power rail is configured to transmit the other of the power voltage and the reference voltage; and

in response to the charged-device model ESD occurring in the integrated circuit, the second ESD protection circuit conducts the ESD charge on the second signal wire to the second power rail.

4. The integrated circuit as claimed in claim 1 , wherein the connecting pad is arranged in a connecting pad layout area of the integrated circuit, and the first internal circuit, the second internal circuit, the second signal wire, and the first ESD protection circuit are arranged in an internal circuit layout area of the integrated circuit.

5. The integrated circuit as claimed in claim 4 , further comprising:

a second ESD protection circuit arranged in the connecting pad layout area, wherein the second ESD protection circuit is coupled to the connecting pad,

the first power rail is configured to transmit one of a power voltage and a reference voltage, and a second power rail of the integrated circuit is configured to transmit the other of the power voltage and the reference voltage, and

in response to an ESD event occurring in the connecting pad, the second ESD protection circuit conducts ESD charge on the connecting pad to at least one of the first power rail and the second power rail.

6. The integrated circuit as claimed in claim 5 , wherein the second ESD protection circuit comprises:

a first diode coupled between the connecting pad and the first power rail; and

a second diode coupled between the connecting pad and the second power rail.

7. The integrated circuit as claimed in claim 5 , wherein the second ESD protection circuit comprises:

an ESD clamping circuit coupled between the first power rail and the second power rail.

8. The integrated circuit as claimed in claim 1 , wherein the first ESD protection circuit comprises:

a first diode circuit, wherein a cathode of the first diode circuit is coupled to the second signal wire, and an anode of the first diode circuit is coupled to the first power rail; and

a second diode circuit, wherein an anode of the second diode circuit is coupled to the second signal wire, and a cathode of the second diode circuit is coupled to the first power rail.

9. The integrated circuit as claimed in claim 8 , wherein the first diode circuit comprises:

a diode, wherein a cathode of the diode is coupled to the cathode of the first diode circuit; and

a transistor, wherein a first end and a control end of the transistor are coupled to an anode of the diode, and a second end of the transistor is coupled to the anode of the first diode circuit.

10. The integrated circuit as claimed in claim 8 , wherein the second diode circuit comprises:

a diode, wherein an anode of the diode is coupled to the anode of the second diode circuit; and

a transistor, wherein a first end and a control end of the transistor are coupled to a cathode of the diode, and a second end of the transistor is coupled to the cathode of the second diode circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 4, 2023
From: CHEN, CHIEN YU
To: NANYA TECHNOLOGY CORPORATION
Reel/Frame 065756/0757 →
Continuity (1)
Related Publication 20250174986A1 · May 29, 2025
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