Embedded backside PCRAM device structure
View Patent ↗An integrated circuit includes a first chip bonded to a second chip. The first chip includes an array of memory cells. Each memory cell includes a transistor and phase change memory element. The transistor is between the phase change memory element and the second chip.
1. An integrated circuit, comprising:
a first chip including a memory cell, the memory cell including:
a transistor including:
a plurality of semiconductor nanosheets;
a gate dielectric surrounding the semiconductor nanosheets;
a gate electrode including a gate metal surrounding the semiconductor nanosheets and separated from the semiconductor nanosheets by the gate dielectric;
a first semiconductor source/drain terminal coupled to the semiconductor nanosheets; and
a second semiconductor source/drain terminal coupled to the semiconductor nanosheets;
a phase change memory element electrically coupled to the transistor; and
a first electrode coupled between the phase change memory element and the transistor and having a top surface coupled to a bottom surface of the first semiconductor source/drain terminal; and
a second chip bonded to the first chip, wherein the transistor is positioned between the phase change memory element and the second chip.
2. The device of claim 1 , wherein the memory cell includes a second electrode coupled to the phase change memory element, the phase change memory element positioned between the first electrode and the second electrode.
3. The device of claim 2 , wherein the first chip further includes:
a first metal line coupled to the second electrode and positioned on a first side of the first chip distal to the second chip; and
a second metal line coupled to the gate electrode and positioned on a second side of the first chip proximal to the second chip.
4. The device of claim 3 , wherein the first metal line is one of a first bitline or a first wordline coupled to the memory cell, and wherein the second metal line is either a second wordline or a second bitline coupled to the memory cell.
5. The device of claim 1 , wherein the first electrode is in contact with one of the semiconductor nanosheets.
6. The device of claim 1 , wherein the phase change material includes GeSbTe.
7. The device of claim 1 , wherein the phase change memory element is a data storage element of the memory cell.
8. The device of claim 1 , wherein the first electrode is a heater element configured to heat the phase change memory element to write or erase data from the phase change element.
9. A device, comprising
a first chip;
a second chip bonded to the first chip and including a semiconductor material;
a transistor in the first chip including:
a first semiconductor source/drain terminal;
a second semiconductor source/drain terminal;
a channel region extending laterally between the source terminal and the drain terminal; and
a gate electrode above the channel region and below the second chip;
a first metal line in the first chip between the transistor and the second chip and coupled to the transistor;
a phase change memory element in the first chip below the channel region and coupled to the transistor, the transistor positioned between the phase change memory element and the second chip, wherein the transistor and the phase change memory element are a memory cell;
a first electrode coupled between the phase change memory element and the transistor and having a top surface coupled to a bottom surface of the first semiconductor source/drain terminal; and
a second metal line in the first chip below the phase change memory cell and coupled to the phase change memory element.
10. The device of claim 9 , further comprising a semiconductor nanosheet below the channel, wherein the first electrode is in contact with the phase change memory element and the semiconductor nanosheet.
11. The device of claim 10 , further comprising a second electrode in contact with the phase change memory element and the second metal line.
12. The device of claim 10 , wherein the first chip is silicon-on-insulator chip.
13. The device of claim 10 , wherein the phase change material includes GeSbTe.
14. The device of claim 10 , wherein the phase change memory element is a data storage element of the memory cell.
15. The device of claim 10 , wherein the first electrode is a heater element configured to heat the phase change memory element to write or erase data from the phase change element.
16. The device of claim 9 , wherein the gate electrode is wrapped around the channel region.
17. A device, comprising:
a first chip including an array of memory cells, each memory cell including:
a transistor including:
a channel region;
a gate electrode above the channel region;
a first semiconductor source/drain terminal in contact with the channel region; and
a second semiconductor source/drain terminal in contact with the channel region, the channel region extending laterally between the source terminal and the drain terminal;
a phase change memory element below the channel region and coupled to either the source terminal or the drain terminal;
an electrode coupled between the phase change memory element and the transistor and having a top surface coupled to a bottom surface of the first semiconductor source/drain terminal; and
a second chip bonded to the first chip above the channel region and including a semiconductor material.
18. The device of claim 17 , comprising a semiconductor nanosheet below the channel region, wherein the electrode is in contact with the phase change memory element and the semiconductor nanosheet.
19. The device of claim 18 , wherein a side surface of the electrode is in contact with the semiconductor nanosheet.
20. The device of claim 17 , wherein the gate electrode is wrapped around the channel region.