Duty-cycle corrector phase shift circuit
View Patent ↗One embodiment of a duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. Another embodiment of a duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. In some instances, the DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.
1. A correcting and phase shifting circuit, comprising:
a voltage-controlled delay line (VCDL) circuit operable to receive a clock input signal;
a duty-cycle corrector (DCC) circuit operably connected to an output of the VCDL circuit and operable to adjust a duty cycle of the clock input signal;
a clock tree connected to the output of the DCC circuit;
a clock tree replica connected to the output of the DCC circuit; and
an error amplifier circuit operably connected to an input of the VCDL circuit and to an output of the clock tree replica.
2. The correcting and phase shifting circuit of claim 1 , further comprising a Low Dropout (LDO) circuit connected to another input of the VCDL circuit.
3. The correcting and phase shifting circuit of claim 1 , further comprising an invertor connected between the DCC circuit and the clock tree.
4. The correcting and phase shifting circuit of claim 1 , further comprising a digital circuit connected to an output of the clock tree replica, wherein the digital circuit is configured to receive the clock input and the clock output.
5. The correcting and phase shifting circuit of claim 4 , further comprising a first Direct Current (DC) sampler circuit and a second DC sampler circuit connected between the digital circuit and the error amplifier.
6. The correcting and phase shifting circuit of claim 5 , further comprising:
a first multiplexer connected between the digital circuit and the first DC sampler circuit; and
a second multiplexer connected between the digital circuit and the second DC sampler circuit.
7. The correcting and phase shifting circuit of claim 5 , wherein the digital circuit is operable to output two pulse signals, and wherein the a first pulse signal is provided to the first DC sampler and the second pulse signal is provided to the second DC sampler.
8. The correcting and phase shifting circuit of claim 1 , wherein the clock tree replica includes two inverters connected in series.
9. A correcting and phase shifting circuit, comprising:
a voltage-controlled delay line (VCDL) circuit operable to receive a clock input signal;
a duty-cycle corrector (DCC) circuit operably connected to an output of the VCDL circuit and operable to adjust a duty cycle of the clock input signal;
a clock buffer connected to the output of the DCC circuit;
a clock buffer replica operable to receive the clock input; and
an error amplifier circuit operably connected to an input of the VCDL circuit and to an output of the clock buffer replica and an output of the clock buffer.
10. The correcting and phase shifting circuit of claim 9 , further comprising a Low Dropout (LDO) circuit connected between the error amplifier and the VCDL circuit.
11. The correcting and phase shifting circuit of claim 9 , further comprising an invertor connected between the DCC circuit and the clock buffer.
12. The correcting and phase shifting circuit of claim 9 , further comprising a digital circuit connected to an output of the clock buffer replica and the output of the clock buffer.
13. The correcting and phase shifting circuit of claim 12 , further comprising a first Direct Current (DC) sampler circuit and a second DC sampler circuit connected between the digital circuit and the error amplifier.
14. The correcting and phase shifting circuit of claim 13 , further comprising:
a first multiplexer connected between the digital circuit and the first DC sampler circuit; and
a second multiplexer connected between the digital circuit and the second DC sampler circuit.
15. A correcting and phase shifting circuit, comprising:
a voltage-controlled delay line (VCDL) circuit operable to receive a clock input signal;
a duty-cycle corrector (DCC) circuit operably connected to an output of the VCDL circuit and operable to adjust a duty cycle of the clock input signal;
a clock buffer connected to the output of the DCC circuit;
an invertor connected between the DCC circuit and the clock buffer;
a phase modulator operable to receive the clock input signal; and
an error amplifier circuit operably connected to an input of the VCDL circuit and to an output of each of the phase modulator and the clock buffer.
16. The correcting and phase shifting circuit of claim 15 , further comprising a Low Dropout (LDO) circuit connected between the error amplifier and the VCDL circuit.
17. The correcting and phase shifting circuit of claim 15 , wherein the DCC circuit is further operable to provide a clock output signal and the clock buffer.
18. The correcting and phase shifting circuit of claim 15 , further comprising a digital circuit connected to an output of the phase modulator and the output of the clock buffer.
19. The correcting and phase shifting circuit of claim 18 , further comprising a first Direct Current (DC) sampler circuit and a second DC sampler circuit connected between the digital circuit and the error amplifier.
20. The correcting and phase shifting circuit of claim 19 , further comprising:
a first multiplexer connected between the digital circuit and the first DC sampler circuit; and
a second multiplexer connected between the digital circuit and the second DC sampler circuit.