Semiconductor package including redistribution substrate and method of manufacturing the same
A semiconductor package includes a redistribution substrate including a conductive structure having a lower conductive pattern and a redistribution structure electrically connected to the lower conductive pattern, on the lower conductive pattern, an insulating structure covering at least a side surface of the redistribution structure, and a protective layer between the lower conductive pattern and the insulating structure, a semiconductor chip on the redistribution substrate, and a lower connection pattern below the redistribution substrate and electrically connected to the lower conductive pattern. The protective layer includes a first portion in contact with at least a portion of an upper surface of the lower conductive pattern, and a second portion in contact with at least a portion of a side surface of the lower conductive pattern.
1. A semiconductor package, comprising:
a redistribution substrate including
a conductive structure having a lower conductive pattern and a redistribution structure electrically connected to the lower conductive pattern,
the redistribution structure being on the lower conductive pattern,
an insulating structure covering at least a side surface of the redistribution structure, and
a protective layer between the lower conductive pattern and the insulating structure;
a semiconductor chip on the redistribution substrate; and
a lower connection pattern below the redistribution substrate and electrically connected to the lower conductive pattern,
wherein the protective layer includes
a first portion in contact with at least a portion of an upper surface of the lower conductive pattern, and
a second portion in contact with at least a portion of a side surface of the lower conductive pattern,
wherein a lower end of the protective layer is located at a level higher than a lower surface of the insulating structure, and
wherein the lower connection pattern is in contact with both the lower end of the protective layer and the lower conductive pattern.
2. The semiconductor package of claim 1 , wherein
a thickness of the first portion of the protective layer between the insulating structure and the lower conductive pattern in a first direction is greater than a thickness of the second portion between the insulating structure and the lower conductive pattern in a second direction,
the first direction is perpendicular to the upper surface of the lower conductive pattern, and
the second direction is perpendicular to the side surface of the lower conductive pattern.
3. The semiconductor package of claim 1 , wherein the lower end of the protective layer, the lower surface of the insulating structure, and a lower surface of the lower conductive pattern are at different levels.
4. The semiconductor package of claim 1 , wherein
a lower surface of the lower conductive pattern is located at a lower level than the lower surface of the insulating structure.
5. The semiconductor package of claim 1 , wherein the protective layer includes a conductive material.
6. The semiconductor package of claim 1 , wherein
the upper surface of the lower conductive pattern is flat,
the lower conductive pattern includes an upper corner region extending from the upper surface of the lower conductive pattern and being an at least partially curved surface, and
the side surface of the lower conductive pattern extends from the upper corner region.
7. The semiconductor package of claim 1 , wherein
the protective layer is a conductive layer,
the redistribution structure includes a redistribution pattern including a redistribution line and a redistribution via,
the redistribution via extends downwardly from a portion of the redistribution line, penetrates through the first portion of the protective layer and contacts the lower conductive pattern, and
the redistribution via has a width less than a width of the lower conductive pattern.
8. The semiconductor package of claim 7 , wherein
the redistribution pattern includes a seed metal layer and a metal material pattern on the seed metal layer, and
the seed metal layer of the redistribution pattern is in contact with the lower conductive pattern.
9. The semiconductor package of claim 1 , further comprising:
an upper connection pattern between the semiconductor chip and the redistribution substrate,
wherein the redistribution substrate further includes an upper conductive pattern on the redistribution structure,
wherein the upper conductive pattern includes
a pad portion located on a level higher than an upper surface of the insulating structure, and
a via portion extending downwardly from at least a portion of the pad portion and electrically connected to the redistribution structure,
wherein the insulating structure covers a side surface of the via portion, and
wherein the upper connection pattern is in contact with the upper conductive
pattern.
10. The semiconductor package of claim 9 , further comprising an encapsulant covering at least a side surface of the semiconductor chip and surrounding a side surface of the upper connection pattern, the encapsulant being between the semiconductor chip and the redistribution substrate.
11. The semiconductor package of claim 9 , further comprising:
an underfill resin surrounding a side surface of the upper connection pattern, between the semiconductor chip and the redistribution substrate; and
an encapsulant covering at least a side surface of the semiconductor chip, the encapsulant being on the redistribution substrate.
12. The semiconductor package of claim 1 , further comprising
a plurality of semiconductor chips, the plurality of semiconductor chips including the semiconductor chip,
the plurality of semiconductor chips are spaced apart from each other in a direction, parallel to an upper surface of the insulating structure,
each semiconductor chip of the plurality of semiconductor chips is electrically connected to the redistribution substrate, and
the redistribution substrate further includes a redistribution connection line electrically connecting at least two semiconductor chips of the plurality of semiconductor chips.
13. The semiconductor package of claim 1 , further comprising:
a first encapsulant covering at least a side surface of the semiconductor chip, the first encapsulant being on the redistribution substrate;
a vertical connection pattern penetrating through the first encapsulant and electrically connected to a portion of the conductive structure of the redistribution substrate; and
an upper semiconductor chip on the first encapsulant and the semiconductor chip.
14. The semiconductor package of claim 13 , further comprising:
an upper redistribution substrate on the first encapsulant,
wherein the upper semiconductor chip is on the upper redistribution substrate,
the upper redistribution substrate includes an upper redistribution pattern electrically connected to the vertical connection pattern, and
the upper redistribution pattern includes an upper redistribution line, and an upper redistribution via extending downwardly from a portion of the upper redistribution line.
15. A semiconductor package, comprising:
a redistribution substrate having a first surface and a second surface that are opposite surfaces in relation to each other;
a semiconductor chip on the first surface of the redistribution substrate;
a lower connection pattern below the second surface of the redistribution substrate; and
an upper connection pattern electrically connecting the redistribution substrate and the semiconductor chip, the upper connection pattern being between the redistribution substrate and the semiconductor chip,
wherein the redistribution substrate includes
a conductive structure, and
an insulating structure covering at least a side surface of the conductive structure,
wherein the conductive structure includes a lower conductive pattern and a redistribution structure,
wherein the lower conductive pattern is electrically connected to the lower connection pattern,
wherein the redistribution structure includes a plurality of redistribution patterns located at different levels on the lower conductive pattern,
wherein the redistribution substrate further includes a protective layer between the lower conductive pattern and the insulating structure,
wherein the protective layer is a conductive layer,
wherein the protective layer includes
a first portion in contact with at least a portion of an upper surface of the lower conductive pattern, and
a second portion in contact with at least a portion of a side surface of the lower conductive pattern,
wherein a lower redistribution pattern among the plurality of redistribution patterns includes a redistribution line, and a redistribution via extending downwardly from a portion of the redistribution line,
wherein the redistribution via penetrates through the first portion of the protective layer and contacts the lower conductive pattern, and
wherein a side surface of the redistribution via is in contact with the first portion of the protective layer and the insulating structure.
16. The semiconductor package of claim 15 , wherein
the conductive structure further includes an upper conductive pattern electrically connected to an upper redistribution pattern among the plurality of redistribution patterns, on the upper redistribution pattern,
the upper connection pattern is in contact with the upper conductive pattern,
the lower connection pattern is in contact with both a lower end of the protective layer and a lower surface of the lower conductive pattern,
in the protective layer, a thickness of the first portion in a first direction is greater than a thickness of the second portion in a second direction,
the first direction is perpendicular to the upper surface of the lower conductive pattern,
the second direction is perpendicular to the side surface of the lower conductive pattern, and
the lower end of the protective layer is located at a level higher than a lower surface of the insulating structure.
17. The semiconductor package of claim 16 , wherein
the lower conductive pattern includes an upper corner region, which extends from the upper surface of the lower conductive pattern and of which at least a portion is a curved surface, and
the side surface of the lower conductive pattern extends from the upper corner region.
18. A semiconductor package, comprising:
a redistribution substrate including
a conductive structure having a lower conductive pattern and a redistribution structure on the lower conductive pattern and electrically connected to the lower conductive pattern,
an insulating structure covering at least a side surface of the redistribution structure, and
a protective layer between the lower conductive pattern and the insulating structure;
a semiconductor chip on the redistribution substrate; and
a lower connection pattern in contact with both the lower conductive pattern and the protective layer, the lower connection pattern being below the redistribution substrate,
wherein a thickness of the lower conductive pattern is in a range of about 3 μm to about 15 μm,
wherein a width of the lower conductive pattern is in a range of about 80 μm to about 300 μm,
wherein a thickness of the protective layer is in a range of about 30 nm to about 300 nm,
wherein a lower end of the protective layer is located at a level higher than a lower surface of the insulating structure, and
wherein a lower surface of the lower conductive pattern is located at a lower level than the lower surface of the insulating structure.
19. The semiconductor package of claim 18 , wherein
the protective layer includes
a first portion in contact with at least a portion of an upper surface of the lower conductive pattern, and
a second portion in contact with at least a portion of a side surface of the lower conductive pattern,
in the protective layer, a thickness of the first portion in a first direction is greater than a thickness of the second portion in a second direction,
the first direction is perpendicular to the upper surface of the lower conductive pattern, and
the second direction is perpendicular to the side surface of the lower conductive pattern.