Semiconductor device
A device includes a channel layer, a gate structure, a first gate spacer, and a second gate spacer. The gate structure wraps around the channel layer. The first gate spacer and the second gate spacer are on opposite sides of the gate structure. The first gate spacer has a first portion and a second portion between the gate structure and the first portion of the first gate spacer, and a dopant concentration of the second portion of the first gate spacer is greater than a dopant concentration of the first portion of the first gate spacer.
1. A device comprising:
a channel layer;
a gate structure wrapping around the channel layer, wherein the gate structure comprises:
an interfacial layer wrapping around the channel layer;
a high-k dielectric layer over the interfacial layer; and
a gate electrode over the high-k dielectric layer; and
a first gate spacer and a second gate spacer on opposite sides of the gate structure, wherein a portion of the high-k dielectric layer is directly beneath the first gate spacer, the first gate spacer has a first portion and a second portion between the gate structure and the first portion of the first gate spacer, and a dopant concentration of the second portion of the first gate spacer is greater than a dopant concentration of the first portion of the first gate spacer.
2. The device of claim 1 , wherein the second portion of the first gate spacer comprises a dopant selected from the group consisting of Al, Hf, La, Sc, Y and a combination thereof.
3. The device of claim 1 , wherein the high-k dielectric layer is in contact with the second portion of the first gate spacer.
4. The device of claim 1 , wherein the high-k dielectric layer is separated from the first portion of the first gate spacer by the second portion of the first gate spacer.
5. The device of claim 1 , wherein the interfacial layer is separated from the second portion of the first gate spacer by the high-k dielectric layer.
6. The device of claim 1 , wherein a thickness of the first portion of the first gate spacer is greater than the second portion of the first gate spacer.
7. The device of claim 1 , wherein a bottom surface of the high-k dielectric layer is spaced apart from the first gate spacer.
8. A device comprising:
a substrate;
an epitaxial layer over the substrate;
an epitaxial nanowire over the epitaxial layer, wherein the epitaxial layer and the epitaxial nanowire are made of different materials; and
a gate structure wrapping around the epitaxial nanowire, wherein the gate structure comprises:
a doped interfacial layer in contact with a bottom surface of the epitaxial nanowire and an inner sidewall of the epitaxial layer;
a high-k dielectric layer wrapping around the doped interfacial layer; and
a gate electrode wrapping around the high-k dielectric layer.
9. The device of claim 8 , wherein the doped interfacial layer comprises a dopant selected from the group consisting of Al, Hf, La, Sc, Y and a combination thereof.
10. The device of claim 8 , wherein the high-k dielectric layer is separated from the epitaxial nanowire by the doped interfacial layer.
11. The device of claim 8 , wherein the doped interfacial layer is in contact with the substrate.
12. The device of claim 8 , further comprising a gate spacer on a sidewall of the gate structure.
13. The device of claim 12 , wherein the gate spacer is in contact with the high-k dielectric layer but spaced apart from the doped interfacial layer.
14. The device of claim 12 , wherein the doped interfacial layer and the gate spacer comprise the same dopants.
15. A device comprising:
a channel layer;
a gate structure surrounding the channel layer and comprising:
an interfacial layer in contact with the channel layer;
a high-k dielectric layer over the interfacial layer; and
a gate electrode over the high-k dielectric layer;
a first gate spacer and a second gate spacer on opposite sides of the gate structure, wherein a portion of the high-k dielectric layer is directly beneath the first gate spacer; and
a dielectric layer directly between the first gate spacer and the channel layer, wherein a thickness of the dielectric layer is greater than a thickness of the interfacial layer.
16. The device of claim 15 , wherein the high-k dielectric layer is in contact with a bottom surface of the first gate spacer and the dielectric layer.
17. The device of claim 15 , wherein the dielectric layer is in contact with a bottom surface of the first gate spacer.
18. The device of claim 15 , wherein the dielectric layer is in contact with the interfacial layer.
19. The device of claim 15 , wherein the interfacial layer comprises a dopant selected from the group consisting of Al, Hf, La, Sc, Y and a combination thereof.
20. The device of claim 15 , wherein the first gate spacer comprises a dopant selected from the group consisting of Al, Hf, La, Sc, Y and a combination thereof.