Analog peak power management for multi-die operations
Methods of peak power management (PPM) for a storage system having multiple memory dies are disclosed. Each memory die includes a first PPM circuit and a second PPM circuit. First PPM circuits of the multiple memory dies are electrically connected to form a first PPM group. Similarly, second PPM circuits are electrically connected to form a second PPM group. Peak power operations can be managed by switching on a first pull-down driver of the first PPM circuit on a selected memory die when a first PPM enablement signal of the first PPM group is zero; waiting for a first delay period; switching on a second pull-down driver of the second PPM circuit on the selected memory die when a second PPM enablement signal of the second PPM group is zero. The first and second PPM enablement signals depend on the current flowing through each pull-down driver in the first and second PPM groups.
1. A system, comprising:
memory dies, each of the memory dies comprising a peak power management (PPM) circuit, each PPM circuit of the memory dies comprising a PPM pad, wherein:
the PPM pad of each PPM circuit is connected with each of the other PPM pads, and
the PPM circuits of the memory dies are configured to change an electrical potential of the PPM pads in response to a change in a number of memory dies performing a peak power operation,
wherein each of the PPM circuits is configured to receive a control signal in response to a peak power operation being performed on a corresponding memory die,
wherein each of the PPM circuits further comprises a first driver and a second driver, and
wherein one second driver corresponding to the number of memory dies performing peak power operations is enabled and other second drivers corresponding to the number of memory dies performing peak power operations are disenabled.
2. The system of claim 1 , wherein the PPM pad is between the first driver and the second driver, a first terminal of the second driver is connected with a first voltage, a second terminal of the second driver and a first terminal of the first driver are connected with the PPM pad, and a second terminal of the first driver is connected with a second voltage lower than the first voltage.
3. The system of claim 2 , wherein a control terminal of the first driver is configured to receive the control signal.
4. The system of claim 2 , wherein the electrical potential of the PPM pads is determined by first currents flowing through first drivers of the PPM circuits.
5. The system of claim 2 , further comprising a memory controller, the memory controller coupled to the memory dies and configured to control the second driver in each PPM circuit of the memory dies.
6. The system of claim 1 , wherein the electrical potential of the PPM pads non-linearly or linearly changes with the number of memory dies performing peak power operation changes.
7. The system of claim 1 , wherein the electrical potential of the PPM pad decreases with the number of memory dies performing peak power operation increases.
8. The system of claim 1 , wherein each of the PPM circuits further comprises an output circuit, the output circuit is connected with the PPM pad, and the output circuit is configured to output the PPM enablement signal.
9. The system of claim 8 , wherein the output circuit comprises a comparator with first input terminal connected to the PPM pad and a second terminal connected to receive the reference voltage.
10. The system of claim 9 , wherein the reference voltage corresponds to a maximum number of memory dies performing peak power operations.
11. A memory die, comprising:
a peak power management (PPM) circuit comprising a first driver, a second driver, and a PPM pad, the PPM pad is between the first driver and the second driver; and
a control circuit, wherein the PPM circuit is configured to receive a control signal from the control circuit in response to a peak power operation being performed on the memory die,
wherein one second driver corresponding to the number of memory dies performing peak power operations is enabled and other second drivers corresponding to the number of memory dies performing peak power operations are disenabled.
12. The memory die of claim 11 , wherein a first terminal of the second driver is connected with a power source, a second terminal of the second driver and a first terminal of the first driver are connected with the PPM pad, and a second terminal of the first driver is connected with a ground voltage.
13. The memory die of claim 12 , wherein the PPM circuit further comprises:
a first resistor between the PPM pad and the first terminal of the first driver; and
a second resistor between the second terminal of the second driver and the PPM pad.
14. The memory die of claim 11 , wherein the PPM circuit further comprises a comparator with a first input terminal connected to the PPM pad and a second input terminal connected to receive the reference voltage.
15. A method for operating memory dies each comprising a peak power management (PPM) circuit, each of PPM circuit comprises a PPM pad, wherein PPM pads of the PPM circuits are connected with each other, the method comprising:
receiving a control signal in response to a peak power operation being performed on a corresponding memory die; and
changing an electrical potential of the PPM pads in response to the control signal,
wherein each of the PPM circuits further comprises a first driver and a second driver, and
wherein one second driver corresponding to the number of memory dies performing peak power operations is enabled and other second drivers corresponding to the number of memory dies performing peak power operations are disenabled.
16. The method of claim 15 , further comprising:
generating, based on the electrical potential of the PPM pads, the PPM enablement signal for managing a number of memory dies performing peak power operation.
17. The method of claim 16 , wherein generating the PPM enablement signal for managing the number of memory dies performing peak power operation further comprising:
comparing the electrical potential of the PPM pads with the reference voltage.
18. The method of claim 17 , wherein the reference voltage corresponds to a maximum number of memory dies performing peak power operations.