IP Library › Granted Patent US 12,394,882
Granted Patent B2
US 12,394,882 · App. 18/359,187 · Granted Aug 19, 2025

Antenna device and camera system

Inventors: Tatsuhito Goden (Tokyo, JP); Yasushi Koyama (Kanagawa, JP); Noriyuki Kaifu (Tokyo, JP)
Assignee: CANON KABUSHIKI KAISHA
H01Q1/2283H01Q21/061H01Q23/00
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Quick Facts
Patent No.
US 12,394,882
App. No.
18/359,187
Granted
Aug 19, 2025
Kind
B2
Abstract

An antenna device includes an antenna array in which a plurality of antennas each including a negative differential resistance element and a resonance circuit are arranged, a voltage bias circuit which applies a voltage to the antenna array, a first shunt element which is connected between the antenna array and the voltage bias circuit in parallel relation to each of the negative differential resistance element and the voltage bias circuit, and in which a first resistor and a first capacitor of the first shunt element are connected in series, and a second shunt element which is connected between the first shunt element and the voltage bias circuit in parallel relation to each of the negative differential resistance element and the voltage bias circuit, and in which a second resistor and a second capacitor of the second shunt element are connected in series.

Claims (94)

1. An antenna device transmitting or receiving an electromagnetic wave, the antenna device comprising:

an antenna array in which a plurality of antennas each including a negative differential resistance element and a resonance circuit are arranged;

a voltage bias circuit which applies a voltage to the antenna array;

a first shunt element which is connected between the antenna array and the voltage bias circuit in parallel relation to each of the negative differential resistance element and the voltage bias circuit, and in which a first resistor and a first capacitor of the first shunt element are connected in series; and

a second shunt element which is connected between the first shunt element and the voltage bias circuit in parallel relation to each of the negative differential resistance element and the voltage bias circuit, and in which a second resistor and a second capacitor of the second shunt element are connected in series, wherein

each of the first shunt element and the second shunt element has a low impedance with respect to a resistance value of the negative differential resistance element used as a reference.

2. The antenna device according to claim 1 ,

wherein expressions (1) to (3) below are satisfied:

Rp+ 1/(2π× f×Cp )< r   (1)

Rc+ 1/(2π× f×Cc )< r   (2)

L /( Cc×r )< Rc   (3)

where r is an absolute value of the resistance value of the negative differential resistance element, Rp is a resistance value of the second resistor, Cp is a capacitance value of the second capacitor, Rc is a resistance value of the first resistor, Cc is a capacitance value of the first capacitor, L is an inductance of a path connecting the first shunt element and the second shunt element, and f is a frequency less than a resonance frequency of the resonance circuit.

3. The antenna device according to claim 1 ,

wherein the inductance L of the path connecting the first shunt element and the second shunt element satisfies an expression (4) below:

L≤ 5 nH  (4)

wherein, in a case where the path is divided into a first portion in which a cross section of the path can be approximated to a circular shape and a second portion in which the cross section of the path can be approximated to a quadrilateral shape, an inductance L 1 of the first portion is calculated according to an expression (5) below, while an inductance L 2 of the second portion is calculated according to an expression (6) below:

L 1=0.2× l 1×[ln(4× l 1/ d )−0.75]  (5)

L 2=0.2× l 2×[ln{2× l 2/( w+h )}+0.2235]×( w+h )/ l 2+0.5]  (6)

where l 1 is a length of the first portion, d is a diameter of a cross section of the first portion, l 2 is a length of the second portion, w is a width of the second portion, and h is a thickness of the second portion.

4. The antenna device according to claim 1 ,

wherein a plurality of pairs of the first shunt elements and the second shunt elements are arranged, and

wherein at least two of the pairs of the first shunt elements and the second shunt elements are placed at positions symmetrical to each other with respect to an axis passing through a center of the antenna array.

5. The antenna device according to claim 4 ,

wherein the two pairs of the first shunt elements and the second shunt elements are arranged such that the antenna array is interposed between the two pairs of the first shunt elements and the second shunt elements.

6. The antenna device according to claim 4 ,

wherein the first shunt elements are arranged on a chip on which the antenna array is to be placed,

wherein the chip is a chip having a quadrilateral shape, and

wherein the second shunt elements included in the respective pairs of the first shunt elements and the second shunt elements are arranged in the vicinities of corners of the chip.

7. The antenna device according to claim 4 ,

wherein the second shunt elements included in the two respective pairs of the first shunt elements and the second shunt elements are connected in parallel.

8. The antenna device according to claim 1 ,

wherein the first shunt element is placed on the chip on which the antenna array is to be placed, and

wherein the second shunt element is placed on a substrate on which the chip is to be placed.

9. The antenna device according to claim 8 ,

wherein the path connecting the first shunt element and the second shunt element includes a first pad placed on the chip and a second pad placed on the substrate, and

wherein a bias voltage is supplied to the antenna array via each of the first pad and the second pad.

10. The antenna device according to claim 9 , further comprising:

a third pad placed on the chip and a fourth pad placed on the substrate,

wherein a ground voltage is supplied to the antenna array via each of the third pad and the fourth pad,

wherein the chip is a chip having a quadrilateral shape,

wherein the bias voltage is supplied from a side of the chip, on which a first side thereof is present, to the antenna array via each of the first pad and the second pad, and

wherein the ground voltage is supplied from a side of the chip, on which a second side thereof different from the first side is present, to the antenna array via each of the third pad and the fourth pad.

11. The antenna device according to claim 9 ,

wherein the first pad and the second pad are connected using a plurality of bonding wires connected in parallel.

12. The antenna device according to claim 8 ,

wherein the second resistor is wiring placed in the substrate.

13. The antenna device according to claim 1 ,

wherein a combined resistance value of the negative differential resistance elements in the antenna array is not more than 1 Ω.

14. The antenna device according to claim 1 ,

wherein a length of the path connecting the first shunt element and the second shunt element is not more than 4 mm.

15. The antenna device according to claim 14 ,

wherein the length of the path connecting the first shunt element and the second shunt element is not more than 2 mm.

16. The antenna device according to claim 1 ,

wherein a frequency band of the electromagnetic wave includes at least a part of a frequency band of at least 30 GHz and not more than 30 THz.

17. The antenna device according to claim 1 ,

wherein the negative differential resistance element is a resonant tunneling diode.

18. The antenna device according to claim 1 ,

wherein the first capacitor is a MIM (Metal-Insulator-Metal) capacitor.

19. The antenna device according to claim 1 , further comprising:

a third shunt element connected in parallel to the negative differential resistance element in the antenna array and including at least a third capacitor.

20. The antenna device according to claim 19 ,

wherein a plurality of the third shunt elements are arranged between the antenna and the antenna.

21. The antenna device according to claim 20 ,

wherein each of the third shunt elements is shared between the two antennas each adjacent to the third shunt element.

22. The antenna device according to claim 19 ,

wherein respective areas or capacitance values of the third capacitor, the first capacitor, and the second capacitor are progressively larger in this order.

23. The antenna device according to claim 19 ,

wherein the number of the third shunt elements is the number of the first shunt elements or more and the number of the second shunt elements or more.

24. The antenna device according to claim 19 ,

wherein the number of the third shunt elements is less than the number of the first shunt elements and less than the number of the second shunt elements.

25. The antenna device according to claim 1 ,

wherein the number of the second shunt elements is the number of the first shunt elements or more.

26. The antenna device according to claim 1 ,

wherein the number of the second shunt elements is less than the number of the first shunt elements.

27. An antenna device transmitting or receiving an electromagnetic wave, the antenna device comprising:

a chip having an antenna array in which a plurality of antennas each including a negative differential resistance element and a resonance circuit are arranged;

a substrate on which the chip is to be placed; and

a voltage bias circuit that applies a voltage to the antenna array, wherein

the chip has:

a first shunt element connected in parallel to each of the negative differential resistance element and the voltage bias circuit and including at least a first capacitor; and

a plurality of pads including at least each of a first pad and a second pad to supply a predetermined voltage to the antenna array,

the substrate has:

a second shunt element connected in parallel to each of the negative differential resistance element and the voltage bias circuit, and including at least a second capacitor, and moreover placed in the substrate, and wherein

the antenna array is located between the first pad and the second pad.

28. The antenna device according to claim 27 , further comprising:

a third shunt element connected in parallel to the negative differential resistance element in the antenna array and including at least a third capacitor.

29. A camera system comprising:

the antenna device according to claim 1 ;

a detection device for detecting the electromagnetic wave transmitted from the antenna device; and

a processing unit that processes a signal from the detection device.

30. A camera system comprising:

the antenna device according to claim 27 ;

a detection device for detecting the electromagnetic wave transmitted from the antenna device; and

a processing unit that processes a signal from the detection device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 28, 2023
From: GODEN, TATSUHITO; KOYAMA, YASUSHI; KAIFU, NORIYUKI
To: CANON KABUSHIKI KAISHA
Reel/Frame 065056/0160 →
Priority Claims (2)
JP 2021-015981 · Feb 3, 2021 · national
JP 2021-199839 · Dec 9, 2021 · national
Continuity (2)
Continuation PCTJP2021047654 · Dec 22, 2021
Related Publication 20230378637A1 · Nov 23, 2023
References Cited (31)
US 7924107B2 · Koyama · 2011 [cited by applicant]
US 9184697B2 · Sekiguchi · 2015 [cited by applicant]
US 9391428B2 · Koyama · 2016 [cited by applicant]
US 9899959B2 · Feiginov · 2018 [cited by applicant]
US 11025199B2 · Kandori · 2021 [cited by applicant]
US 11283406B2 · Kandori · 2022 [cited by applicant]
US 11451193B2 · Kandori · 2022 [cited by applicant]
US 11626839B2 · Koyama · 2023 [cited by examiner]
US 11637530B2 · Fujimoto · 2023 [cited by examiner]
US 11770102B2 · Kandori · 2023 [cited by applicant]
US 20140266477A1 · Sekiguchi · 2014 [cited by applicant]
US 20200266762A1 · Kandori · 2020 [cited by applicant]
US 20220173515A1 · Koyama · 2022 [cited by applicant]
US 20220317331A1 · Goden · 2022 [cited by applicant]
US 20230110775A1 · Numata · 2023 [cited by applicant]
US 20230207500A1 · Koyama · 2023 [cited by applicant]
US 20230208359A1 · Koyama · 2023 [cited by applicant]
US 20230258793A1 · Itsuji · 2023 [cited by applicant]
US 20230262312A1 · Koyama · 2023 [cited by applicant]
US 20230335885A1 · Yukimasa · 2023 [cited by applicant]
US 20230335898A1 · Koyama · 2023 [cited by applicant]
JP 2014200065A · 2014 [cited by applicant]
JP 2015180047A · 2015 [cited by applicant]
JP 2015180049A · 2015 [cited by applicant]
JP 202057739A · 2020 [cited by applicant]
JP 2020136910A · 2020 [cited by applicant]
International Search Report issued Mar. 1, 2022 in corresponding PCT Application No. PCT/JP2021/047654(English translation included). [cited by applicant]
U.S. Appl. No. 18/474,264, filed Sep. 26, 2023 by Yasushi Koyama. [cited by applicant]
Structure-Simplified Resonant-Tunneling-Diode Teraherz Oscillator Without Metal-Insulator-Metal Capacitors, Journal of Infrared, Millimeter, and Terahertz Waves (2020) 41:1498-1507, published on Aug. 29, 2020, by Ta Van… [cited by applicant]
High-Efficiency Bias Stabilization for Resonant Tunneling Diode Oscillators, IEEE Transactions on Microwave Theory and Techniques, vol. 67, No. 8, pp. 3449-3454, published Aug. 2019, by Andrei Catalin Cornescu, et al. [cited by applicant]
Japanese Office Action issued Jun. 3, 2025 during prosecution of related Japanese Application No. 2021-199839. (English-language machine translation included). [cited by applicant]
Cited By (1)
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