Integrated circuit package and method
A method includes attaching semiconductor devices to an interposer structure, attaching the interposer structure to a first carrier substrate, attaching integrated passive devices to the first carrier substrate, forming an encapsulant over the semiconductor devices and the integrated passive devices, debonding the first carrier substrate, attaching the encapsulant and the semiconductor devices to a second carrier substrate, forming a first redistribution structure on the encapsulant, the interposer structure, and the integrated passive devices, wherein the first redistribution structure contacts the interposer structure and the integrated passive devices, and forming external connectors on the first redistribution structure.
1. A package comprising:
a device substrate; wherein the device substrate comprises integrated circuits;
a first surface-mount device (SMD) attached to the first side of the device substrate;
a device structure attached to a first side of the device substrate, the device structure comprising:
a first interposer;
a second interposer;
a plurality of first semiconductor devices attached to the first interposer;
a plurality of second semiconductor devices attached to the second interposer;
a first redistribution structure connected to the first interposer and the second interposer, wherein the first redistribution structure is attached to the first side of the device substrate with solder bumps; and
a first encapsulant on the first redistribution structure, the first encapsulant separating the first interposer from the second interposer; and
a second encapsulant covering the first SMD and surrounding the device structure.
2. The package of claim 1 , wherein the device substrate is a second redistribution structure.
3. The package of claim 1 , wherein the first redistribution structure physically contacts the first side of the device substrate.
4. The package of claim 1 , wherein a layer of underfill material is between the plurality of first semiconductor devices and the first interposer.
5. The package of claim 1 further comprising a second surface-mount device (SMD) attached to the first side of the device substrate, wherein the first SMD and the second SMD have different heights.
6. The package of claim 1 , wherein top surfaces of the device structure and the second encapsulant are level.
7. The package of claim 1 , wherein the second encapsulant extends between the first SMD and the device substrate.
8. A device comprising:
a first redistribution structure;
a second redistribution structure physically and electrically contacting a first side of the first redistribution structure;
a plurality of interposers physically and electrically contacting the second redistribution structure;
a respective plurality of semiconductor dies connected to each interposer of the plurality of interposers;
a first encapsulant over the second redistribution structure, wherein the first encapsulant encapsulates the plurality of interposers;
a first integrated passive device physically and electrically contacting the first side of the first redistribution structure;
a second integrated passive device physically and electrically contacting the first side of the first redistribution structure, wherein the first integrated passive device and the second integrated passive device have different heights above the first side of the first redistribution structure; and
a second encapsulant over the first side of the first redistribution structure, wherein the second encapsulant encapsulates the first integrated passive device and the first encapsulant.
9. The device of claim 8 , wherein each interposer of the plurality of interposers comprises a respective interconnect structure, wherein the respective plurality of semiconductor dies is connected to the respective interconnect structure.
10. The device of claim 8 , wherein the semiconductor dies of each plurality of semiconductor dies are respectively surrounded by a molding material.
11. The device of claim 10 , wherein top surfaces of the semiconductor dies and a top surface of the molding material are coplanar.
12. The device of claim 9 , wherein the first encapsulant and the second redistribution structure have coplanar sidewalls.
13. The device of claim 8 , wherein top surfaces of the second encapsulant and at least one semiconductor die are coplanar.
14. The device of claim 8 , wherein the first redistribution structure is wider than the second redistribution structure.
15. A device comprising:
a plurality of device packages connected to a first side of a first interconnect structure, wherein each device package comprises:
an interposer;
a plurality of semiconductor devices connected to the interposer; and
a first encapsulant respectively surrounding each semiconductor device of the plurality of semiconductor devices;
a second encapsulant respectively surrounding each device package of the plurality of device packages;
a device substrate connected to a second side of the first interconnect structure;
a passive device connected to the device substrate adjacent the first interconnect structure; and
a third encapsulant encapsulating the first interconnect structure, the plurality of device packages, and the passive device, wherein the third encapsulant and the device substrate have coplanar sidewalls.
16. The device of claim 15 , wherein the device substrate comprises a second interconnect structure.
17. The device of claim 15 , wherein top surfaces of the first encapsulant and the second encapsulant are coplanar.
18. The device of claim 15 , wherein each interposer directly contacts the first interconnect structure.
19. The device of claim 15 , wherein top surfaces of the first encapsulant and the third encapsulant are coplanar.
20. The device of claim 15 , wherein the second encapsulant respectively surrounds each interposer of the plurality of device packages.