Semiconductor structure and manufacturing method thereof
The present disclosure relates to the technical field of semiconductors, and proposes a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a base and a communication portion, the communication portion being located in the base and including a first connection layer, a second connection layer, and a third connection layer, the second connection layer being located on the first connection layer, and the third connection layer being located on the second connection layer; wherein the first connection layer, the second connection layer, and the third connection layer include different conductive materials, and thermal expansion coefficients of the second connection layer and the third connection layer are both less than a thermal expansion coefficient of the first connection layer.
1. A semiconductor structure, comprising:
a base comprising a silicon substrate;
a communication portion, the communication portion being located in the base and the communication portion comprising a first connection layer, a second connection layer, and a third connection layer, the second connection layer being located on the first connection layer, and the third connection layer being located on the second connection layer;
wherein a top of the second connection layer is higher than an upper surface of the silicon substrate, a bottom of the second connection layer is lower than an upper surface of the silicon substrate;
wherein a sum of a heights of the second connection layer and the third connection layer is less than one half of a height of the first connection layer; and
wherein a thermal expansion coefficient of the second connection layer is less than a thermal expansion coefficient of the third connection layer, and the thermal expansion coefficient of the third connection layer is less than a thermal expansion coefficient of the first connection layer; the first connection layer is made of copper, the second connection layer is made of graphene, and the third connection layer is made of tungsten.
2. The semiconductor structure according to claim 1 , wherein the second connection layer is located in the first connection layer.
3. The semiconductor structure according to claim 2 , wherein the third connection layer is located in the first connection layer.
4. The semiconductor structure according to claim 3 , wherein in a direction perpendicular to the base, a projection of the second connection layer coincides with a projection of the third connection layer;
wherein a top of the third connection layer is flush with a top of the first connection layer.
5. The semiconductor structure according to claim 1 , further comprising:
an insulation layer, the insulation layer covering the upper surface of the silicon substrate and covering an outer surface of the communication portion.
6. The semiconductor structure according to claim 5 , wherein a functional layer is formed in the silicon substrate, and the bottom of the second connection layer is lower than a lower surface of the functional layer.
7. The semiconductor structure according to claim 5 , wherein a portion of the second connection layer entering the silicon substrate has a depth greater than or equal to 1 μm.
8. The semiconductor structure according to claim 1 , wherein the second connection layer has a diameter of 200 nm to 10 μm, and the second connection layer has a depth of 1 μm to 20 μm.
9. A method for forming the semiconductor structure of claim 1 , comprising:
providing a base comprising a silicon substrate;
forming a communication portion on the base, the communication portion comprising a first connection layer, a second connection layer, and a third connection layer, the second connection layer being formed on the first connection layer, and the third connection layer being formed on the second connection layer;
wherein a top of the second connection layer is higher than an upper surface of the silicon substrate, a bottom of the second connection layer is lower than an upper surface of the silicon substrate;
wherein a sum of a heights of the second connection layer and the third connection layer is less than one half of a height of the first connection layer; and
wherein a thermal expansion coefficient of the second connection layer is less than a thermal expansion coefficient of the third connection layer, and the thermal expansion coefficient of the third connection layer is less than a thermal expansion coefficient of the first connection layer; the first connection layer is made of copper, the second connection layer is made of graphene, and the third connection layer is made of tungsten.
10. The method according to claim 9 , wherein an opening is formed in the first connection layer, and the second connection layer and the third connection layer are sequentially formed in the opening.
11. The method according to claim 9 , wherein the first connection layer, the second connection layer, and the third connection layer are sequentially formed in the base;
wherein in a direction perpendicular to the base, a projection of the second connection layer coincides with, a projection of the third connection layer.