IP Library › Granted Patent US 12,400,989
Granted Patent B2
US 12,400,989 · App. 18/428,934 · Granted Aug 26, 2025

Arrangement of power-grounds in package structures

Inventors: Ting-Yu Yeh (Hsinchu, TW); Chun-Hua Chang (Zhubei, TW); Fong-Yuan Chang (Hsinchu, TW); Jyh Chwen Frank Lee (Palo Alto, CA)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L24/20H01L24/19H01L21/568H01L24/13H01L2224/13024H01L2224/19H01L2224/221
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,400,989
App. No.
18/428,934
Granted
Aug 26, 2025
Kind
B2
Abstract

A structure includes a redistribution structure, which includes a bottom layer and a plurality of upper layers over the bottom layer. The redistribution structure also includes a power-ground macro extending from a topmost layer in the plurality of upper layers to a bottommost layer in the plurality of upper layers, and a metal pad in the bottom layer and overlapped by the power-ground macro. The metal pad is electrically disconnected from the power-ground macro.

Claims (58)

1. A method comprising:

placing a device die over a carrier;

encapsulating the device die in an encapsulant;

planarizing the encapsulant to reveal metal pads in the device die; and

forming a redistribution structure over the device die and the encapsulant, wherein the redistribution structure comprises a bottom layer in contact with the device die, and a plurality of upper layers over the bottom layer, and wherein the redistribution structure comprises:

a first power-ground macro extending from a topmost layer in the plurality of upper layers to a bottommost layer in the plurality of upper layers; and

a first metal pad in the bottom layer and overlapped by the first power-ground macro, wherein the first metal pad is electrically disconnected from the first power-ground macro.

2. The method of claim 1 , wherein the redistribution structure further comprises:

a second power-ground macro extending from the topmost layer in the plurality of upper layers to the bottommost layer in the plurality of upper layers; and

a second metal pad in the bottom layer and overlapped by the second power-ground macro, wherein the second metal pad is electrically connected to the second power-ground macro.

3. The method of claim 1 , wherein the forming the first power-ground macro comprises forming a solder region in the topmost layer in the plurality of upper layers.

4. The method of claim 1 further comprising de-bonding the carrier from the device die and the encapsulant.

5. The method of claim 1 , wherein the plurality of upper layers comprise four layers.

6. The method of claim 1 further comprising:

before the redistribution structure is formed, copying the first power-ground macro from a library and placing the first power-ground macro into a design layout; and

laying out the first metal pad in the design layout, wherein the redistribution structure is formed to implement the design layout.

7. The method of claim 6 , wherein the placing the first power-ground macro and the laying out the first metal pad are performed in separate steps.

8. The method of claim 6 further comprising:

placing a plurality of power macros and a plurality of ground macros into the design layout;

laying out a blanket metal pad overlapped by the plurality of power macros and the plurality of ground macros; and

patterning the blanket metal pad in the design layout as a first plurality of metal plates and a second plurality of metal plates separated from each other.

9. The method of claim 8 , wherein one of the first plurality of metal plates encircles the second plurality of metal plates.

10. The method of claim 9 further comprising

laying out a first via in the design layout and connecting the one of the first plurality of metal plates to one of the power macros; and

laying out a plurality of second vias in the design layout and connecting the second plurality of metal plates to respective ones of the plurality of ground macros.

11. The method of claim 8 , wherein the blanket metal pad is in a layer higher than the first metal pad.

12. A method comprising:

placing a device die over a carrier;

encapsulating the device die in an encapsulant;

planarizing the encapsulant to reveal metal pads in the device die; and

forming a redistribution structure over the device die and the encapsulant, wherein forming the redistribution structure comprises:

forming a plurality of dielectric layers and a plurality of conductive layers in the plurality of dielectric layers, wherein the forming the plurality of conductive layers comprises:

forming a bottom layer of conductive features, wherein the bottom layer comprises:

at least one first conductive feature; and

at least one second conductive feature, wherein patterns of the at least one first conductive feature are different from the at least one second conductive feature;

forming a first power-ground macro overlapping the at least one first conductive feature; and

forming a second power-ground macro overlapping the at least one second conductive feature.

13. The method of claim 12 further comprising:

copying and placing the first power-ground macro and the second power-ground macro from a library into a design layout; and

laying out the bottom layer of conductive features in the design layout, wherein the redistribution structure is formed to implement the design layout.

14. The method of claim 12 , wherein the first power-ground macro and the second power-ground macro are identical to each other.

15. The method of claim 12 , wherein the metal pads of the device die comprise metal pillars.

16. The method of claim 12 , wherein the bottom layer of conductive features has a top surface level with a top surface of one of the plurality of dielectric layers.

17. A method comprising:

placing a device die over a carrier;

encapsulating the device die in an encapsulant;

planarizing the encapsulant to reveal metal pads in the device die; and

forming a redistribution structure over the device die and the encapsulant, wherein the redistribution structure comprises:

a plurality of lower dielectric layers over the device die;

a first metal pad in a bottom layer of the plurality of lower dielectric layers;

a plurality of upper dielectric layers over the plurality of lower dielectric layers; and

a power-ground macro extending from a topmost layer in the plurality of upper dielectric layers to a bottommost layer in the plurality of upper dielectric layers, wherein the first metal pad is overlapped by the power-ground macro, and wherein the first metal pad is electrically disconnected from the power-ground macro.

18. The method of claim 17 , wherein the redistribution structure comprises:

a second metal pad in the bottom layer and vertically misaligned from the power-ground macro, wherein the second metal pad is electrically connected to the power-ground macro.

19. The method of claim 17 , wherein the redistribution structure is formed layer-by-layer.

20. The method of claim 17 further comprising:

copying the power-ground macro from a library and placing the power-ground macro into a design layout; and

laying out the first metal pad in the design layout in a step that is separate from the copying and placing, wherein the redistribution structure is formed to implement the design layout.

Continuity (3)
Division 17394213 · Aug 4, 2021
Provisional Application 63139940 · Jan 21, 2021
Related Publication 20240178177A1 · May 30, 2024
References Cited (24)
US 8549460B2 · Law et al. · 2013 [cited by applicant]
US 10103124B2 · Kawaminami · 2018 [cited by applicant]
US 10796980B2 · Yokoyama · 2020 [cited by applicant]
US 10886224B2 · Gerousis et al. · 2021 [cited by applicant]
US 10957662B2 · Wu · 2021 [cited by applicant]
US 10957679B2 · Lee et al. · 2021 [cited by applicant]
US 11101209B2 · Liu et al. · 2021 [cited by applicant]
US 11309246B2 · Dabral et al. · 2022 [cited by applicant]
US 20080098340A1 · Oh · 2008 [cited by applicant]
US 20110260318A1 · Eisenstadt · 2011 [cited by applicant]
US 20140110856A1 · Lin · 2014 [cited by examiner]
US 20160155692A1 · Dosluoglu · 2016 [cited by applicant]
US 20170063079A1 · Gu et al. · 2017 [cited by applicant]
US 20190157233A1 · Fillion · 2019 [cited by examiner]
US 20210018773A1 · Woodgate et al. · 2021 [cited by applicant]
US 20210202391A1 · Chun et al. · 2021 [cited by applicant]
US 20210391270A1 · Chun · 2021 [cited by examiner]
US 20220367210A1 · Lin · 2022 [cited by examiner]
CN 107799493A · 2018 [cited by applicant]
DE 112021000867T5 · 2022 [cited by applicant]
JP 2019176008A · 2019 [cited by applicant]
KR 20110004280A · 2011 [cited by applicant]
KR 20200135151A · 2020 [cited by applicant]
TW 201915624A · 2019 [cited by applicant]