Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device includes forming a stacked structure by stacking gate layers and interlayer insulating layers alternately on a substrate; and forming a channel structure passing through the stacked structure in a vertical direction, wherein the forming a channel structure includes forming an opening by etching the stacked structure; forming a gate insulating layer covering a side surface of the opening; forming a variable resistive material layer on the gate insulating layer; changing an oxygen vacancy concentration in a region of the variable resistive material layer by performing a plasma treatment process or an annealing process on the variable resistive material layer; forming a core insulating pattern covering the variable resistive material layer and filling at least a portion of the opening; and forming a pad pattern on the core insulating pattern.
1. A method of manufacturing a semiconductor device, comprising:
forming a stacked structure by stacking gate layers and interlayer insulating layers alternately on a substrate; and
forming a channel structure that passes through the stacked structure in a vertical direction,
wherein the forming a channel structure includes,
forming an opening by etching the stacked structure,
forming a gate insulating layer covering at least a side surface of the opening,
forming a variable resistive material layer on the gate insulating layer,
changing an oxygen vacancy concentration in a region of the variable resistive material layer by performing one or both of a plasma treatment process on the variable resistive material layer or an annealing process on the variable resistive material layer,
forming a core insulating pattern covering the variable resistive material layer and filling at least a portion of the opening, after performing the one or both of plasma treatment process or the annealing process, and
forming a pad pattern on the core insulating pattern.
2. The method of claim 1 , wherein the variable resistive material layer is formed by the one or both of the plasma treatment process or the annealing process to include a channel region including oxygen vacancies at a first concentration, and a data storage region including oxygen vacancies at a second concentration, less than the first concentration.
3. The method of claim 2 , wherein the channel region of the variable resistive material layer is formed to contact the gate insulating layer and to extend along a side surface of the gate insulating layer, and
the data storage region of the variable resistive material layer is formed to contact the core insulating pattern and to extend along a side surface of the core insulating pattern.
4. The method of claim 2 , wherein the data storage region of the variable resistive material layer is formed to be farther from the side surface of the opening, compared to the channel region.
5. The method of claim 1 , wherein the variable resistive material layer is formed of a transition metal oxide.
6. The method of claim 1 , wherein the variable resistive material layer is formed of at least one of hafnium oxide (HfO), zinc oxide (ZnO), indium oxide (InO), gallium oxide (GaO), tin oxide (SnO), copper oxide (CuO), molybdenum oxide (MoO), hafnium-silicon oxide (HSO), hafnium-zinc oxide (HZO), indium-zinc oxide (IZO), indium-gallium oxide (IGO), indium-tin oxide (ITO), indium-gallium-zinc oxide (IGZO), or indium-tin-zinc oxide (ITZO).
7. The method of claim 1 , wherein the annealing process includes one or both of a thermal annealing process or a laser annealing process.
8. The method of claim 1 , wherein the forming a variable resistive material layer on the gate insulating layer comprises:
forming a first layer including a transition metal oxide on the gate insulating layer; and
forming a second layer including a transition metal oxide on the first layer.
9. The method of claim 8 , wherein the one or both of plasma treatment process or the annealing process is performed on at least one of the first layer or the second layer.
10. The method of claim 9 , wherein an oxygen vacancy concentration in the transition metal oxide of the first layer increases in the first layer by the plasma treatment process.
11. The method of claim 9 , wherein an oxygen vacancy concentration in the transition metal oxide of the second layer decreases in the second layer by the annealing process.
12. The method of claim 1 , wherein the forming a variable resistive material layer on the gate insulating layer comprises:
forming a variable resistive material capping layer filling the opening; and
etching a central region of the variable resistive material capping layer to form the variable resistive material layer extending along a side surface of the gate insulating layer and having a specific thickness from the side surface of the gate insulating layer.
13. The method of claim 1 , wherein the forming a core insulating pattern comprises:
forming a first core insulating layer conformally on the variable resistive material layer;
removing a portion of the first core insulating layer and a portion of the variable resistive material layer from upper portions thereof, respectively;
forming a second core insulating layer filling the opening and contacting the first core insulating layer; and
forming the core insulating pattern by removing a portion of the first core insulating layer and a portion of the second core insulating layer from upper portions thereof, and
the forming a pad pattern comprises:
forming a pad space by removing an upper portion of the core insulating pattern; and
forming the pad pattern by depositing a conductive material in the pad space.
14. A method of manufacturing a semiconductor device, comprising:
forming a stacked structure by stacking gate layers and interlayer insulating layers alternately on a substrate; and
forming a channel structure passing through the stacked structure in a vertical direction,
wherein the forming a channel structure includes,
forming an opening by etching the stacked structure,
forming a gate insulating layer covering at least a side surface of the opening;
forming a variable resistive material layer on the gate insulating layer and including a first region and a second region,
changing an oxygen vacancy concentration in either of the first region or the second region,
forming a core insulating pattern filling at least a portion of the opening, and
forming a pad pattern on the core insulating pattern.
15. The method of claim 14 , wherein the variable resistive material layer is formed of a transition metal oxide.
16. The method of claim 14 , wherein the changing an oxygen vacancy concentration in either of the first region or the second region comprises decreasing an oxygen vacancy concentration in the second region, compared to an oxygen vacancy concentration in the first region,
wherein the first region is in contact with the gate insulating layer, and
the second region is in contact with the core insulating pattern.
17. The method of claim 14 , wherein the variable resistive material layer has an oxygen vacancy concentration profile gradually decreasing along a width of the variable resistive material layer in a direction from the gate insulating layer toward a central region of the channel structure.
18. The method of claim 14 , further comprising:
forming a separation opening passing through the stacked structure;
removing the gate layers through the separation opening; and
forming gate electrodes by filling regions from which the gate layers are removed with a conductive material.
19. A method of manufacturing a semiconductor device, comprising:
forming a stacked structure by stacking gate layers and interlayer insulating layers alternately on a substrate; and
forming a channel structure passing through the stacked structure in a vertical direction,
wherein the forming a channel structure comprises,
forming an opening by etching the stacked structure,
forming a gate insulating layer in the opening,
forming a variable resistive material capping layer filling the opening and contacting the gate insulating layer,
etching a central region of the variable resistive material capping layer to form a variable resistive material layer extending along a side surface of the gate insulation layer and having a specific thickness from the side surface of the gate insulation layer,
changing an oxygen vacancy concentration in a region of the variable resistive material layer by performing one or both of a plasma treatment process on the variable resistive material layer or an annealing process on the variable resistive material layer;
forming a core insulating pattern that covers the variable resistive material layer and that fills at least a portion of the opening, after performing the one or both of the plasma treatment process or the annealing process; and
forming a pad pattern on the core insulating pattern.
20. The method of claim 19 , wherein the annealing process includes one or both of a thermal annealing process or a laser annealing process,
the variable resistive material layer is formed by the plasma treatment process or the annealing process to include a channel region including oxygen vacancies at a first concentration, and a data storage region including oxygen vacancies at a second concentration, less than the first concentration,
wherein the channel region is formed in a portion of the variable resistive material layer contacting the gate insulating layer, and
the data storage region is formed in a portion of the variable resistive material layer contacting the core insulating pattern.