IP Library Granted Patent US 12,412,836
Granted Patent B2
US 12,412,836 · App. 17/662,870 · Granted Sep 9, 2025

Backside power plane

Inventors: Ruilong Xie (Niskayuna, NY); Nicholas Anthony Lanzillo (Wynantskill, NY); Hosadurga Shobha (Niskayuna, NY); Lawrence A. Clevenger (Saratoga Springs, NY); Huai Huang (Clifton Park, NY)
Assignee: International Business Machines Corporation
H01L23/5286H01L21/76897H01L23/5226H10D30/6757H10D84/0149H10D84/038H10D62/121
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Quick Facts
Patent No.
US 12,412,836
App. No.
17/662,870
Granted
Sep 9, 2025
Kind
B2
Abstract

Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a first power plane electrically connected to a first plurality of via-to-backside power planes (VBPPs), a second power plane, and a plurality of pass through vias electrically connecting the second power plane to a second plurality of VBPPs, wherein the plurality of pass through vias pass through the first power plane.

Claims (25)

1. A semiconductor structure, comprising:

a first power plane electrically connected to a first plurality of entirely metalized via-to-backside power planes (VBPPs) each comprising a horizontal portion directly connected to one transistor of a plurality of first transistors;

a second power plane; and

a plurality of pass through vias electrically connecting the second power plane to a second plurality of entirely metalized VBPPs, wherein the plurality of pass through vias pass through the first power plane and each VBPP comprises a horizontal portion directly connected to one transistor of a plurality of second transistors.

2. The semiconductor structure of claim 1 , further comprising a dielectric plane between the first power plane and the second power plane.

3. The semiconductor structure of claim 2 , wherein the first power plane contacts a first side of the dielectric plane and the second power plane contacts a second side of the dielectric plane.

4. The semiconductor structure of claim 1 , further comprising a spacer between the pass through via and the first power plane.

5. The semiconductor structure of claim 1 , wherein the first power plane is configured to supply a V DD signal and the second power plane is configured to supply a V SS signal.

6. The semiconductor structure of claim 1 , wherein the first plurality of VBPPs comprise a first height, the second plurality of VBPPs comprise a second height that is less than the first height.

7. The semiconductor structure of claim 1 , further comprising:

a first transistor device comprising a first type of semiconductor connected to one of the first plurality of VBPPs; and

a second transistor device comprising a second type of semiconductor different from the first type of semiconductor connected to one of the second plurality of VBPPs.

8. A semiconductor structure, comprising:

a first transistor device of a first semiconductor type;

a second transistor device of a second semiconductor type;

a first power plane electrically connected to the first transistor device by a first entirely metalized via-to-backside power plane (VBPP), wherein the first VBPP is directly connected to the first power plane and comprises a horizontal portion directly connected to the first transistor; and

a second power plane electrically connected to the second transistor device by a second entirely metalized VBPP directly connected to a pass through via that passes through the first power plane and comprises a horizontal portion directly connected to the second transistor.

9. The semiconductor structure of claim 8 , further comprising a spacer between the pass through via and the first power plane.

10. The semiconductor structure of claim 8 , further comprising a dielectric plane between the first power plane and the second power plane.

11. The semiconductor structure of claim 10 , wherein the first power plane contacts a first side of the dielectric plane and the second power plane contacts a second side of the dielectric plane.

12. The semiconductor structure of claim 8 , wherein the first power plane and the second power plane are formed on a backside of the semiconductor structure.

13. The semiconductor structure of claim 8 , wherein the first power plane is configured to supply a V DD signal and the second power plane is configured to supply a V SS signal.

14. The semiconductor structure of claim 8 ,

wherein the first VBPP comprises a first height and

the second VBPP comprises a second height that is less than the first height.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2022
From: XIE, RUILONG; LANZILLO, NICHOLAS ANTHONY; SHOBHA, HOSADURGA; CLEVENGER, LAWRENCE A.; HUANG, HUAI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 059889/0657 →
Continuity (1)
Related Publication 20230369219A1 · Nov 16, 2023
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