Implantations for forming source/drain regions of different transistors
A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.
1. A method comprising:
forming a first gate stack on a sidewall and a top surface of a first protruding fin;
forming a first gate spacer on a sidewall of the first gate stack;
forming a second gate stack on a sidewall and a top surface of a second protruding fin;
forming a second gate spacer on a sidewall of the second gate stack;
performing a first implantation process on a first semiconductor region aside of the first gate stack with a p-type dopant or an n-type dopant to form a first implanted region, wherein the first implanted region extends lower than the first gate spacer, wherein an edge of the first implanted region is flush with a first sidewall of the first gate spacer; and
performing a second implantation process on a second semiconductor region aside of the second gate stack to form a second implanted region, wherein the second implanted region is on a same side of the second gate stack as the second gate spacer, and the second implanted region is horizontally spaced apart from the second gate spacer.
2. The method of claim 1 further comprising:
after the first implantation process, forming an Inter-Layer Dielectric (ILD) contacting the first gate spacer and the second gate spacer, wherein the first implantation process is performed before the ILD is formed, and the second implantation process is performed after the ILD is formed.
3. The method of claim 2 further comprising:
forming a first contact opening and a second contact opening in the ILD to reveal the first implanted region and the second implanted region, respectively; and
forming an implantation mask, wherein during the second implantation process, the first contact opening is filled by the implantation mask, and the second contact opening is exposed.
4. The method of claim 3 , wherein the second contact opening is spaced apart from the first gate spacer by a portion of the ILD.
5. The method of claim 4 , wherein the first contact opening is spaced apart from the first gate spacer by a portion of the ILD.
6. The method of claim 1 , wherein the first gate stack and the second gate stack are comprised in a longer-channel transistor and a shorter-channel transistor, respectively.
7. The method of claim 6 , wherein the longer-channel transistor is a transistor in a Static Random-Access Memory (SRAM) cell, and the shorter-channel transistor is a core transistor.
8. The method of claim 1 , wherein a first dopant implanted by the first implantation process is implanted shallower than a second dopant implanted by the second implantation process.
9. The method of claim 1 , wherein a first dopant implanted by the first implantation process is implanted to substantially a same depth as a second dopant implanted by the second implantation process.
10. The method of claim 1 , wherein a first dopant implanted by the first implantation process has a same conductivity type as a second dopant implanted by the second implantation process.
11. A method comprising:
forming a first gate stack and a second gate stack on semiconductor regions, wherein a first width of the first gate stack is greater than a second width of the second gate stack;
forming a first gate spacer on a sidewall of the first gate stack;
forming a second gate spacer on a sidewall of the second gate stack;
performing a first implantation process on a first semiconductor region on a side of the first gate stack to form a first implanted region, wherein a sidewall the first gate spacer is exposed during the first implantation process;
forming an Inter-Layer Dielectric (ILD) contacting the first gate spacer and the second gate spacer;
forming a first contact opening and a second contact opening in the ILD to reveal the first semiconductor region and a second semiconductor region, respectively;
forming an implantation mask; and
performing a second implantation process on the second semiconductor region on a side of the second gate stack to form a second implanted region, where during the second implantation process, the implantation mask fills the first contact opening, and the second implantation process is performed through the second contact opening, and wherein during the second implantation process, all sidewalls of the second gate spacer are protected from being exposed.
12. The method of claim 11 , wherein during the first implantation process, the second semiconductor region is masked from the first implantation process, and during the second implantation process, the first semiconductor region is masked from the second implantation process.
13. The method of claim 11 , wherein a first dopant introduced by the first implantation process has a same conductivity type as a second dopant introduced by the second implantation process.
14. The method of claim 11 further comprising forming the first semiconductor region and the second semiconductor region comprising:
etching portions of the semiconductor regions to form recesses; and
epitaxially growing the first semiconductor region and the second semiconductor region simultaneously from the recesses.
15. The method of claim 11 , wherein a same dopant is implanted by the first implantation process and the second implantation process.
16. A method comprising:
forming a first transistor comprising:
forming a first gate stack and a second gate stack parallel to each other;
forming a first gate spacer and a second gate spacer on a sidewall of the first gate stack and the second gate stack, respectively;
epitaxially growing a first semiconductor region between the first gate spacer and the second gate spacer, wherein the first semiconductor region comprises a first top surface extending from a first edge of the first gate spacer to a second edge of the second gate spacer; and
performing a first implantation process to implant the first semiconductor region with a first dopant, wherein a first implanted region is formed in the first semiconductor region by the first implantation process, and wherein in the first implantation process, an entirety of the first top surface of the first semiconductor region is implanted; and
forming a second transistor comprising:
forming a third gate stack and a fourth gate stack parallel to each other;
forming a third gate spacer and a fourth gate spacer on a sidewall of the third gate stack and the fourth gate stack, respectively;
epitaxially growing a second semiconductor region between the third gate spacer and the fourth gate spacer, wherein the second semiconductor region comprises a second top surface extending from a third edge of the third gate spacer to a fourth edge of the fourth gate spacer; and
performing a second implantation process to implant the second semiconductor region with a second dopant of a same conductivity type as the first dopant, wherein a second implanted region is formed in the second semiconductor region by the second implantation process, and wherein in the second implantation process, a part of a second top surface of the second semiconductor region is masked from being implanted.
17. The method of claim 16 , wherein during the second implantation process, the part of the second top surface of the second implanted region receiving the second dopant is between opposing portions of an inter-layer dielectric.
18. The method of claim 16 , wherein the first transistor has a first channel length, and the second transistor has a second channel length smaller than the first channel length.
19. The method of claim 16 , wherein in the second implantation process, the part of the second top surface of the second semiconductor region is masked by an inter-layer dielectric.
20. The method of claim 16 , wherein the second implantation process is performed through a contact opening in the inter-layer dielectric.