Device having a gate electrode wrapping around semiconductor layers and proximate to a dielectric fin
A device according to the present disclosure includes a fin structure disposed on a substrate and including a stack of semiconductor layers that are separated from each other, a dielectric fin disposed on the substrate, a spacer layer disposed on a sidewall of the dielectric fin and extending below the dielectric fin such that the spacer layer prevents the dielectric fin from interfacing with the substrate, an interfacial layer wrapping around each semiconductor layer of the stack, a gate dielectric layer disposed on the interfacial layer wrapping around each semiconductor layer of the stack, and a gate electrode layer including a first portion wrapping around the gate dielectric layer disposed on the interfacial layer and a second portion extending along the spacer layer disposed on the dielectric fin. An airgap extends between the first portion of the gate electrode layer and the second portion of the gate electrode layer.
1. A device comprising:
a fin structure disposed on a substrate, the fin structure including a stack of semiconductor layers that are separated from each other;
a dielectric fin disposed on the substrate;
a spacer layer disposed on a sidewall of the dielectric fin and extending below the dielectric fin such that the spacer layer prevents the dielectric fin from interfacing with the substrate;
an interfacial layer wrapping around each semiconductor layer of the stack;
a gate dielectric layer disposed on the interfacial layer wrapping around each semiconductor layer of the stack, the gate dielectric layer extending to the spacer layer disposed on the sidewall of the dielectric fin; and
a gate electrode layer including a first portion wrapping around the gate dielectric layer disposed on the interfacial layer and a second portion extending along the spacer layer disposed on the sidewall of the dielectric fin, wherein an airgap extends between the first portion of the gate electrode layer and the second portion of the gate electrode layer,
wherein the fin structure includes a portion of the substrate having a top surface, and
wherein the airgap extends below the top surface of the portion of the substrate.
2. The device of claim 1 , wherein the interfacial layer interfaces with the top surface of the portion of the substrate.
3. The device of claim 1 , wherein the substrate includes a surface that extends from the portion of the substrate to under the dielectric fin, and
wherein the gate dielectric layer interfaces with the surface.
4. The device of claim 1 , wherein the stack of semiconductor layers includes a first semiconductor layer that is adjacent to a second semiconductor and separate by a first distance, the first distance being measured in a first direction that is substantially perpendicular to a top surface of the substrate,
wherein the spacer layer is separated from one of the first and second semiconductor layers by a second distance, the second distance being measured in a second direction that is substantially parallel to the top surface of the substrate, and
wherein the second distance is at least 2 nm greater than the first distance.
5. The device of claim 1 , wherein the gate electrode layer includes a first electrode layer having a first type of conductivity and a second electrode layer having a second type of conductivity that is opposite the first type of conductivity.
6. The device of claim 1 , wherein the spacer layer extends from the substrate along an entire length of a sidewall surface of the dielectric fin.
7. The device of claim 1 , wherein the gate dielectric layer extends from the substrate along an entire length of a sidewall surface of the spacer layer.
8. The device of claim 1 , wherein the dielectric fin comprises SiCN, SiOC, SiOCN, HfO 2 , ZrO 2 , HfAlO x , HfSiO x , or Al 2 O 3 .
9. A device comprising:
a substrate having a protrusion;
a first elongated semiconductor layer disposed over the protrusion;
a second elongated semiconductor layer disposed over the first elongated semiconductor layer, wherein the second elongated semiconductor layer is spaced apart from the first elongated semiconductor layer by a first distance measured in a first direction that is substantially perpendicular to a top surface of the substrate;
a dielectric fin disposed on the substrate, the dielectric fin having a first sidewall and an opposing second sidewall such that a bottom surface of the dielectric fin extends from the first sidewall to the second sidewall;
a spacer disposed directly on the first sidewall, the second sidewall and the bottom surface of the dielectric fin, wherein the spacer is separated from one of the first and second elongated semiconductor layers by a second distance, the second distance being measured in a second direction that is substantially parallel to the top surface of the substrate; and
a gate electrode layer including a first portion wrapping around the first and second elongated semiconductor layers and a second portion extending along a sidewall of the spacer, wherein an airgap extends between the first portion of the gate electrode layer and the second portion of the gate electrode layer,
wherein top surfaces of the spacer and the dielectric fin are coplanar.
10. The device of claim 9 , further comprising:
an interfacial layer wrapping around the first and second elongated semiconductor layers, wherein the interfacial layer does not extend to the spacer; and
a gate dielectric layer disposed on the interfacial layer wrapping around the first and second elongated semiconductor layers and extending continuously to the sidewall of the spacer.
11. The device of claim 10 , wherein the gate dielectric layer, the first portion of the gate electrode layer, and the second portion of the gate electrode layer extend to the same height above the substrate.
12. The device of claim 9 , wherein the gate electrode layer includes a p-type work function layer selected from the group consisting of TiN, TaN, TaSN, Ru, Mo, Al, WN, WCN ZrSi 2 , MoSi 2 , TaSi 2 , and NiSi 2 .
13. The device of claim 9 , wherein the gate electrode layer includes a n-type work function layer selected from the group consisting of Ti, Al, Ag, Mn, Zr, TiAl, TiAIC, TiAlSiC, TaC, TaCN, TaSiN, TaAl, TaAIC, TaSiAIC, and TiAIN.
14. The device of claim 9 , wherein the spacer and the dielectric fin extend to the same above the substrate.
15. A device comprising,
a dielectric fin extending over a substrate;
a spacer disposed on a sidewall of the dielectric fin and extending below the dielectric fin such that the spacer prevents the dielectric fin from interfacing with the substrate;
a first channel layer disposed over the substrate and adjacent a first sidewall of the dielectric fin;
a second channel layer disposed over the first channel layer, wherein there is a first distance between the first channel layer and the second channel layer;
a third channel layer disposed over the substrate and adjacent an opposing second sidewall of the dielectric fin, wherein there is a second distance between the second sidewall of the dielectric fin and an end of the third channel layer;
a first metal layer disposed over the first channel layer, the second channel layer, and the third channel layer; and
a second metal layer disposed over the third channel layer.
16. The device of claim 15 , wherein the first distance is measured along a first direction, wherein the second distance is measured along a second direction, and wherein the first direction is perpendicular to the second direction.
17. The device of claim 16 , wherein the second distance is at least 2 nm greater than the first distance.
18. The device of claim 15 , wherein the first metal layer is different than the second metal layer.
19. The device of claim 15 , further comprising:
a dielectric layer disposed between the first channel layer and the first metal layer.
20. The device of claim 15 , wherein top surfaces of the dielectric fin and the spacer are coplanar.