Semiconductor device and method of forming the same
View Patent ↗A semiconductor device includes a substrate, a stack of semiconductor nanosheets, a dielectric wall, and a gate structure. The substrate includes a nanosheet mesa, and the stack of semiconductor nanosheets is disposed on the nanosheet mesa. The dielectric wall crosses through the nanosheet mesa and the stack of semiconductor nanosheets. The gate structure wraps the stack of semiconductor nanosheets and crosses over the dielectric wall, wherein a top of the dielectric wall has a recess.
1. A semiconductor device, comprising:
a substrate comprising a nanosheet mesa
a stack of semiconductor nanosheets disposed on the nanosheet mesa;
a dielectric wall crossing through the nanosheet mesa and the stack of semiconductor nanosheets; and
a gate structure wrapping the stack of semiconductor nanosheets and crossing over the dielectric wall,
wherein a top of the dielectric wall has a recess.
2. The semiconductor device of claim 1 , wherein a bottom surface of the recess is higher than a top surface of the stack of semiconductor nanosheets.
3. The semiconductor device of claim 1 , wherein the recess is a hole, and the gate structure fills the hole.
4. The semiconductor device of claim 1 , wherein the recess is a groove perpendicular to an extension direction of the nanosheet mesa.
5. The semiconductor device of claim 1 , further comprising:
an n-type epitaxial layer disposed at a first side of the dielectric wall; and
a p-type epitaxial layer disposed at a second side of the dielectric wall.
6. The semiconductor device of claim 1 , further comprising: a vertical gate contact disposed on the recess.
7. A semiconductor device, comprising:
a substrate;
a dielectric wall disposed on the substrate;
a first stack of semiconductor nanosheets disposed at a first side of the dielectric wall on the substrate;
a second stack of semiconductor nanosheets disposed at a second side of the dielectric wall on the substrate; and
a gate structure wrapping the first stack of semiconductor nanosheets and the second stack of semiconductor nanosheets,
wherein a top of the dielectric wall has a recess, and
the gate structure covers the top of the dielectric wall and fills in the recess.
8. The semiconductor device of claim 7 , wherein a bottom surface of the recess is higher than a top surface of the first stack of semiconductor nanosheets and a top surface of the second stack of semiconductor nanosheets.
9. The semiconductor device of claim 7 , wherein the top of the dielectric wall is bowl-shaped.
10. The semiconductor device of claim 7 , wherein the top of the dielectric wall has a U-shaped cross section.
11. The semiconductor device of claim 10 , wherein the top of the dielectric wall has sidewalls parallel to an extension direction of the gate structure in a plan view.
12. The semiconductor device of claim 7 , further comprising:
an n-type epitaxial layer disposed at the first side of the dielectric wall; and
an p-type epitaxial layer disposed at the second side of the dielectric wall.
13. The semiconductor device of claim 7 , further comprising: a vertical gate contact disposed on the recess.
14. A method of forming a semiconductor device, comprising
providing a substrate comprising a nanosheet mesa
forming a stack of semiconductor nanosheets disposed on the nanosheet mesa;
forming a dielectric wall crossing through the nanosheet mesa and the stack of semiconductor nanosheets, wherein a top of the dielectric wall has a recess; and
forming a gate structure wrapping the stack of semiconductor nanosheets and crossing over the dielectric wall.
15. The method of claim 14 , wherein a step of forming the dielectric wall is followed by a step of forming a dummy gate structure.
16. The method of claim 15 , wherein the step of forming the dielectric wall comprises etching the top of the dielectric wall using an etching mask with a hole.
17. The method of claim 15 , wherein the step of forming the dielectric wall comprises etching the top of the dielectric wall using an etching mask with a trench.
18. The method of claim 14 , wherein a step of forming the dielectric wall follows a step of forming a dummy gate structure.
19. The method of claim 18 , further comprising
forming an inter layer dielectric (ILD) to cover a fill in on the dummy gate structure;
performing a planarization process on the ILD until the dummy gate structure is exposed; and
removing the dummy gate structure to expose the top of the dielectric wall.
20. The method of claim 19 , wherein the step of forming the dielectric wall comprises etching the top of the dielectric wall using the ILD as an etching mask.