Forksheet transistor with dual depth late cell boundary cut
Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a first pair of field effect transistors (FETs). Additionally, the semiconductor structure includes a second pair of FETs. Further, the semiconductor structure includes a shallow gate cut that separates a first pair of gates, a first pair of channels, and a first pair of source/drain (S/D) epitaxies of the first pair of FETs. Additionally, the first pair of S/D epitaxies are wired to a backside power rail (BPR) by a backside contact. Further, the semiconductor structure includes a deep gate cut that separates a second pair of S/D epitaxies of the second pair of FETs. Additionally, one of the second pair of S/D epitaxies is wired to a back end of line (BEOL) interconnect via a frontside contact. Further, another of the second pair of S/D epitaxies is wired to the BPR by a backside contact.
1 . A semiconductor structure comprising:
a first pair of field effect transistors (FETs);
a second pair of FETs;
a shallow gate cut, wherein the shallow gate cut separates:
a first pair of gates of the first pair of FETs;
a first pair of channels of the first pair of FETs; and
a first pair of source/drain epitaxies of the first pair of FETs, wherein the first pair of source/drain epitaxies are wired to a backside power rail by a first backside contact; and
a deep gate cut, wherein the deep gate cut separates a second pair of source/drain epitaxies of the second pair of FETs, and wherein one of the second pair of source/drain epitaxies is wired to a back end of line (BEOL) interconnect via a frontside contact, and wherein a second of the second pair of source/drain epitaxies is wired to the backside power rail by a second backside contact.
2 . The semiconductor structure of claim 1 , wherein a portion of the second backside contact has a horizontal component that overlaps with a region of the deep gate cut.
3 . The semiconductor structure of claim 2 , wherein the horizontal component increases a contact area between the second backside contact and the backside power rail.
4 . The semiconductor structure of claim 1 , further comprising a sacrificial placeholder that is disposed under the one of the second pair of source/drain epitaxies that is wired to the BEOL interconnect.
5 . The semiconductor structure of claim 1 , wherein the first pair of FETs comprises a pair of n-type FETs.
6 . The semiconductor structure of claim 5 , wherein the second pair of FETs comprises a pair of p-type FETs.
7 . The semiconductor structure of claim 1 , wherein the first backside contact comprises a merged contact that spans a region of the shallow gate cut.
8 . The semiconductor structure of claim 1 , comprising a plurality of forksheet FETs.
9 . A semiconductor structure comprising:
a plurality of forksheet field effect transistors (FETs), comprising:
a first pair of FETs; and
a second pair of FETs;
a shallow gate cut, wherein the shallow gate cut separates:
a first pair of gates of the first pair of FETs;
a first pair of channels of the first pair of FETs; and
a first pair of source/drain epitaxies of the first pair of FETs, wherein the first pair of source/drain epitaxies are wired to a backside power rail by a first backside contact; and
a deep gate cut, wherein the deep gate cut separates a second pair of source/drain epitaxies of the second pair of FETs, and wherein one of the second pair of source/drain epitaxies is wired to a back end of line (BEOL) interconnect via a frontside contact, and wherein a second of the second pair of source/drain epitaxies is wired to the backside power rail by a second backside contact, and wherein a portion of the second backside contact has a horizontal component that overlaps with a region of the deep gate cut.
10 . The semiconductor structure of claim 9 , wherein the horizontal component increases a contact area between the second backside contact and the backside power rail.
11 . The semiconductor structure of claim 9 , further comprising a sacrificial placeholder that is disposed under the one of the second pair of source/drain epitaxies that is wired to the BEOL interconnect.
12 . The semiconductor structure of claim 9 , wherein the first pair of FETs comprises a pair of n-type FETs.
13 . The semiconductor structure of claim 12 , wherein the second pair of FETs comprises a pair of p-type FETs.
14 . The semiconductor structure of claim 9 , wherein the first backside contact comprises a merged contact that spans a region of the shallow gate cut.
15 . A method for fabricating a semiconductor device, the method comprising:
forming a nanosheet comprising:
merged field effect transistors; and
a sacrificial placeholder under a first source/drain epitaxy;
forming a deep gate cut through a first pair of source/drain epitaxies that comprise the first source/drain epitaxy, wherein the deep gate cut cuts through the first pair of source/drain epitaxies, and wherein the first source/drain epitaxy is wired to a back end of line (BEOL) interconnect through a frontside contact, and wherein a second source/drain epitaxy of the first pair of source/drain epitaxies is wired to a backside power rail (BSPR) via a first backside contact; and
forming a shallow gate cut through a second pair of source/drain epitaxies, wherein the second pair of source/drain epitaxies is wired to the BSPR via a second backside contact.
16 . The method of claim 15 , further comprising:
forming a middle of line (MOL) interconnect;
forming the BEOL interconnect; and
bonding a carrier wafer to the BEOL interconnect.
17 . The method of claim 16 , further comprising:
flipping the carrier wafer; and
removing a substrate.
18 . The method of claim 17 , further comprising forming a self-aligned backside contact landing over the sacrificial placeholder, wherein the self-aligned backside contact is self-aligned to a region of the deep gate cut.
19 . The method of claim 15 , further comprising:
removing an additional sacrificial placeholder; and
forming a second backside contact in place of the removed additional sacrificial placeholder.
20 . The method of claim 15 , further comprising filling the shallow gate cut and the deep gate cut with a dielectric material.