Epi growth uniformity with source/drain placeholder
A semiconductor device includes a nanosheet stack on a substrate. A first source/drain is on a first side of the nanosheet stack and a second source/drain is on an opposing side of the nanosheet stack. A backside contact includes a first contact end on a first end of the first source/drain and an opposing second contact end in electrical communication with a backside power distribution network. A frontside contact includes a first contact end on a first end of the second source/drain and an opposing second contact end in electrical communication with a backend of line (BEOL) interconnect. A placeholder extends from an opposing second end of the second source/drain.
1. A method of fabrication a semiconductor device, the method comprising:
patterning a semiconductor nanosheet stack formed on semiconductor substrate to define a channel region between a first designated source/drain region and a second designated source/drain region;
forming a first source/drain trench in a first portion of the semiconductor substrate located in the first designated source/drain channel region and forming a second source/drain trench in a second portion of the semiconductor substrate located in the second designated source/drain channel region;
extending a depth of the second source/drain trench to define a deep trench while maintaining a depth of the first source/drain trench;
forming a placeholder element in the first source/drain trench and a deep trench placeholder element in the deep trench; and
forming a first source/drain on the placeholder element and a second source/drain on the deep trench placeholder element,
wherein the semiconductor substrate includes an etch stop layer interposed between a lower portion of the semiconductor substrate and an upper portion of the semiconductor substrate, and wherein extending a depth of the second source/drain trench further comprises etching the upper portion of the semiconductor substrate until stopping on the etch stop layer to define the depth of the deep trench.
2. The method of claim 1 , wherein forming the first and second placeholder elements comprises:
filling the first source/drain trench and the deep trench with a placeholder material; and
recessing the placeholder material until the upper surface of the placeholder material disposed in the first source/drain trench and the deep trench reach a targeted depth.
3. The method of claim 2 , wherein the targeted depth forms a recessed surface of the placeholder material that is co-planar with an upper surface of the semiconductor substrate.
4. The method of claim 2 , wherein the targeted depth forms a recessed surface of the placeholder material that is above an upper surface of the semiconductor substrate.
5. The method of claim 2 , wherein forming a first source/drain and the second source/drain includes epitaxially growing the first source/drain from the placeholder element and epitaxially growing the second source/drain from the deep trench placeholder element.
6. The method of claim 1 , further comprising replacing the deep trench placeholder element with a backside contact that establishes electrical connection with the second source drain.
7. The method of claim 6 , further comprising forming a gate around the channel region.
8. The method of claim 7 , wherein the backside contact is below a base of the gate.
9. The method of claim 7 , wherein the backside contact extend above a base of the gate.
10. A semiconductor device comprising:
a substrate extending along a first axis to define a length, a second axis orthogonal to the first axis to define a width, and a third axis orthogonal to the first and second axes to define a height;
a nanosheet stack on the substrate, the nanosheet stack defining channels of the semiconductor device;
a first source/drain on a first side of the nanosheet stack and a second source/drain on an opposing side of the nanosheet stack;
a backside contact including a first contact end on a first end of the first source/drain and an opposing second contact end in electrical communication with a backside power distribution network;
a frontside contact including a first contact end on a first end of the second source/drain and an opposing second contact end in electrical communication with a backend of line (BEOL) interconnect;
a placeholder extending along the third axis from an opposing second end of the second source/drain, the placeholder having a height that is less than a height of the backside contact.
11. The semiconductor device of claim 10 , wherein the first source/drain extends along the third axis to define a first source/drain height and the second source/drain extends along the third axis to define a second source/drain height matching the first source/drain height.
12. The semiconductor device of claim 10 , wherein the backside contact extends along the third axis between the first source/drain and the backside power distribution network to define a contact height, and wherein the placeholder extends between the second source/drain and the backside power distribution network to define a placeholder height.
13. The semiconductor device of claim 12 , wherein the placeholder height is less than the contact height.
14. A semiconductor device comprising:
a substrate extending along a first axis to define a length, a second axis orthogonal to the first axis to define a width, and a third axis orthogonal to the first and second axes to define a height;
a nanosheet stack on the substrate, the nanosheet stack including a plurality of individual nanosheets defining channels of the semiconductor device;
a gate stack on the substrate and wrapping around the individual nanosheets;
a first source/drain on a first side of the nanosheet stack and a second source/drain on an opposing side of the nanosheet stack;
a backside contact extending from a first contact end in electrical communication with a backside power distribution network to a second contact end located completely below the gate stack and contacting the first source/drain;
a frontside contact extending from a first contact end in electrical communication with a backend of line (BEOL) interconnect to an opposing second contact end contacting a first end of the second source/drain; and
a placeholder extending along the third axis from a first end to an opposing second end located below the gate stack and contacting an opposing second end of the second source/drain.
15. The semiconductor device of claim 14 , wherein the first source/drain extends along the third axis to define a first source/drain height and the second source/drain extends along the third axis to define a second source/drain height matching the first source/drain height.
16. The semiconductor device of claim 15 , wherein the backside contact extends along the third axis between the first source/drain and the backside power distribution network to define a contact height.
17. The semiconductor device of claim 16 , wherein the placeholder extends between the second source/drain and the backside power distribution network to define a placeholder height.
18. The semiconductor device of claim 17 , wherein the placeholder height is less than the contact height.