Semiconductor memory device having a bit line contact disposed in the substrate
View Patent ↗The present disclosure provides a semiconductor device and a method of fabricating the same, which includes a substrate, a resistor structure, a bit line structure, and a bit line contact. The substrate has an active area and a plurality of isolating regions. The resistor structure is disposed on the isolating regions, and includes a first semiconductor layer, a first capping layer, a first spacer. The bit line structure is disposed on the substrate to intersect the active area and the isolating regions, and includes a second semiconductor layer, a first conductive layer, a second capping layer, and a second spacer. The bit line contact is disposed in the substrate to partially extend into the second semiconductor layer, wherein the bit line contact and the first semiconductor layer include a same semiconductor material.
1. A semiconductor memory device, comprising:
a substrate having an active area and a plurality of isolating regions;
a resistor structure, disposed on the isolating regions, comprising:
a first semiconductor layer;
a first capping layer, disposed on the first semiconductor layer; and
a first spacer, disposed on sidewalls of the first semiconductor layer and the first capping layer;
a bit line structure, disposed on the substrate to intersect the active area and the isolating regions, and the bit line structure comprising:
a second semiconductor layer;
a first conductive layer, disposed on the second semiconductor layer;
a second capping layer, disposed on the first conductive layer; and
a second spacer, physically contacting sidewalls of the second semiconductor layer, the first conductive layer, the second capping layer and the second spacer; and
a bit line contact, disposed in the substrate to partially extend into the second semiconductor layer, wherein the bit line contact and the first semiconductor layer comprise a same semiconductor material.
2. The semiconductor memory device according to claim 1 , wherein the resistor structure further comprises a third semiconductor layer, the first semiconductor layer and the third semiconductor layer comprise different semiconductor materials, and the third semiconductor layer and the second semiconductor layer comprises a same semiconductor material.
3. The semiconductor memory device according to claim 2 , wherein the first semiconductor layer is embedded in the third semiconductor layer and is partially extended into the substrate.
4. The semiconductor memory device according to claim 3 , further comprising:
a plurality of plugs electrically connected to the first semiconductor layer respectively.
5. The semiconductor memory device according to claim 3 , further comprising:
a plurality of plugs electrically connected to the third semiconductor layer respectively.
6. The semiconductor memory device according to claim 3 , wherein the first semiconductor layer comprises a plurality of portions which are separated disposed from each other.
7. The semiconductor memory device according to claim 2 , wherein the third semiconductor layer is disposed on the first semiconductor layer.
8. The semiconductor memory device according to claim 7 , further comprising:
a plurality of plugs electrically connected to the first semiconductor layer and the third semiconductor layer respectively.
9. The semiconductor memory device according to claim 1 , further comprising:
a second conductive layer and a third capping layer, sequentially disposed on the first capping layer, the third capping layer and the second capping layer comprises a same material; and
a plurality of plugs disposed on the substrate, one of the plugs physically contacting the first semiconductor layer of the resistor structure, and another one of the plugs physically contacting the first conductive layer of the bit line structure.
10. The semiconductor memory device according to claim 1 , further comprising:
an interlayer dielectric layer disposed on the substrate, a top surface of the interlayer dielectric layer is coplanar with a top surface of the second capping layer, and the interlayer dielectric layer covers the resistor structure.
11. The semiconductor memory device according to claim 1 , wherein a top surface of the first spacer is lower than a top surface of the second spacer, and the first capping layer and the second capping layer comprise different materials.
12. The semiconductor memory device according to claim 1 , further comprising:
a plurality of plugs disposed on the substrate, one of the plugs physically contacting the first semiconductor layer of the resistor structure, and another one of the plugs physically contacting the first conductive layer of the bit line structure.