Semiconductor memory device
A semiconductor memory device including a substrate including an active pattern that includes a first source/drain region and a second source/drain region; an insulating layer on the substrate; a line structure on the insulating layer and extending in a first direction to cross the active pattern, the line structure penetrating the insulating layer on the first source/drain region and including a bit line electrically connected to the first source/drain region; and a contact spaced apart from the line structure and electrically connected to the second source/drain region, wherein the bit line includes a first portion vertically overlapped with the first source/drain region; and a second portion vertically overlapped with the insulating layer, and wherein a lowermost level of a top surface of the first portion of the bit line is at a level lower than a lowermost level of a top surface of the second portion of the bit line.
1. A semiconductor memory device, comprising:
a substrate including an active pattern that includes a first source/drain region and a second source/drain region;
an insulating layer on the substrate;
a line structure on the insulating layer and extending in a first direction to cross the active pattern, the line structure penetrating the insulating layer on the first source/drain region and including a bit line electrically connected to the first source/drain region; and
a contact spaced apart from the line structure and electrically connected to the second source/drain region,
wherein the bit line includes:
a first portion vertically overlapped with the first source/drain region; and
a second portion vertically overlapped with the insulating layer, and
wherein a lowermost level of a top surface of the first portion of the bit line is at a level lower than a lowermost level of a top surface of the second portion of the bit line.
2. The semiconductor memory device as claimed in claim 1 , wherein a largest width of the first portion of the bit line is larger than a largest width of the second portion of the bit line.
3. The semiconductor memory device as claimed in claim 1 , wherein:
the contact includes:
an upper portion at a level higher than the first portion of the bit line; and
a lower portion in contact with the second source/drain region and at a level lower than the upper portion, and
a width of the upper portion is larger than a width of the lower portion.
4. The semiconductor memory device as claimed in claim 1 , wherein the line structure further includes:
a conductive pattern penetrating the insulating layer and coupled to the first source/drain region; and
a barrier pattern between the conductive pattern and the bit line.
5. The semiconductor memory device as claimed in claim 4 , wherein:
the barrier pattern includes:
a first portion vertically overlapped with the first source/drain region; and
a second portion vertically overlapped with the insulating layer, and
a lowermost level of a top surface of the first portion of the barrier pattern is at level lower than a lowermost level of a top surface of the second portion of the barrier pattern.
6. The semiconductor memory device as claimed in claim 5 , wherein a width of the first portion of the barrier pattern is larger than a width of the second portion of the barrier pattern.
7. The semiconductor memory device as claimed in claim 4 , wherein:
the conductive pattern includes a contact portion coupled to the first source/drain region, and
a width of the contact portion is substantially equal to a width of the first portion of the bit line.
8. The semiconductor memory device as claimed in claim 4 , wherein the barrier pattern is in contact with the insulating layer.
9. The semiconductor memory device as claimed in claim 1 , wherein the bit line penetrates the insulating layer and is in contact with the first source/drain region.
10. The semiconductor memory device as claimed in claim 1 , further comprising a pad pattern between the second source/drain region and the insulating layer,
wherein the contact penetrates the insulating layer and is in contact with the pad pattern.
11. A semiconductor memory device, comprising:
a substrate including a first active pattern, the first active pattern including a first source/drain region and a second source/drain region;
a device isolation layer on the substrate and filling a first trench defining the first active pattern;
an insulating layer on the device isolation layer;
a line structure on the insulating layer, crossing the first active pattern, and extending in a first direction, the line structure including:
a conductive pattern penetrating the insulating layer and being coupled to the first source/drain region,
a barrier pattern on the conductive pattern, and
a bit line on the barrier pattern;
a gate electrode extending in a second direction, crossing the first active pattern, and crossing a region between the first and second source/drain regions;
a spacer on a side surface of the line structure; and
a contact spaced apart from the line structure by the spacer and electrically connected to the second source/drain region,
wherein each of the bit line and the barrier pattern includes:
a first portion vertically overlapped with the first source/drain region; and
a second portion vertically overlapped with the insulating layer, and
wherein a largest width of the first portion of the bit line is larger than a largest width of the second portion of the bit line.
12. The semiconductor memory device as claimed in claim 11 , wherein a width of the first portion of the barrier pattern is larger than a width of the second portion of the barrier pattern.
13. The semiconductor memory device as claimed in claim 11 , wherein:
the conductive pattern includes a contact portion coupled to the first source/drain region, and
a width of the contact portion is substantially equal to a width of the first portion of the bit line.
14. The semiconductor memory device as claimed in claim 11 , wherein a lowermost level of a top surface of the first portion of the bit line is at a level lower than a lowermost level of a top surface of the second portion of the bit line.
15. The semiconductor memory device as claimed in claim 11 , wherein:
the substrate further includes a second active pattern,
each of the first and second active patterns has a long axis in a third direction,
the first and second active patterns are adjacent to each other in the third direction,
the device isolation layer fills a second trench between the first active pattern and the second active pattern, and
the second trench is deeper than the first trench.
16. A semiconductor memory device, comprising:
a substrate including an active pattern having a long axis in a first direction, the active pattern including a first source/drain region and a pair of second source/drain regions, the pair of second source/drain regions being spaced apart from each other in the first direction with the first source/drain region interposed therebetween;
a device isolation layer on the substrate and filling a first trench defining the active pattern;
a pair of gate electrodes extending in a second direction and crossing the active pattern, each gate electrode of the pair of gate electrodes being in a second trench between the first and second source/drain regions;
a gate dielectric layer between each of the pair of gate electrodes and the active pattern;
a gate capping layer on each of the pair of gate electrodes and filling the second trench;
an insulating layer on the substrate;
a line structure on the insulating layer, crossing the active pattern, and extending in a third direction, the line structure including:
a conductive pattern penetrating the insulating layer and being coupled to the first source/drain region,
a bit line on the conductive pattern, and
a barrier pattern between the bit line and the conductive pattern;
a pair of spacers on opposite side surfaces of the line structure, respectively;
contacts respectively coupled to the pair of second source/drain regions and being spaced apart from the line structure by the pair of spacers;
landing pads on the contacts;
first electrodes on the landing pads, respectively;
a second electrode on the first electrodes; and
a dielectric layer between the first electrodes and the second electrode,
wherein the bit line of the line structure includes:
a first portion vertically overlapped with the first source/drain region; and
a second portion vertically overlapped with the insulating layer, and
wherein a lowermost level of a top surface of the first portion of the bit line is at a level lower than a lowermost level of a top surface of the second portion of the bit line.
17. The semiconductor memory device as claimed in claim 1 , wherein:
the contact includes:
an upper portion at a level higher than the first portion of the bit line; and
a lower portion in contact with the second source/drain region and at a level lower than the upper portion, and
a width of the upper portion is larger than a width of the lower portion.
18. The semiconductor memory device as claimed in claim 16 , wherein a largest width of the first portion of the bit line is larger than a largest width of the second portion of the bit line.
19. The semiconductor memory device as claimed in claim 16 , wherein:
the barrier pattern includes:
a first portion vertically overlapped with the first source/drain region; and
a second portion vertically overlapped with the insulating layer, and
a lowermost level of a top surface of the first portion of the barrier pattern is at a level lower than a lowermost level of a top surface of the second portion of the barrier pattern.
20. The semiconductor memory device as claimed in claim 16 , wherein the bit line includes molybdenum (Mo) or ruthenium (Ru).