Single-chip optical transceiver
An optoelectronic device includes a first semiconductor die, having first front and rear surfaces and including at least one avalanche photodetector configured to output electrical pulses in response to photons incident on the first front surface. A second semiconductor die has a second front surface, which is bonded to the first rear surface, and a second rear surface, and includes a photodetector receiver analog circuit coupled to the at least one avalanche photodetector and an emitter driver circuit configured to drive a pulsed optical emitter. A third semiconductor die has a third front surface, which is bonded to the second rear surface, and a third rear surface, and includes logic circuits coupled to control the photodetector receiver analog circuit and the emitter driver circuit and to receive and process the electrical pulses output by the at least one avalanche photodetector.
1. An optoelectronic device, comprising:
a first semiconductor die, having first front and rear surfaces, and comprising at least one avalanche photodetector configured to output electrical pulses in response to photons incident on the first front surface;
a second semiconductor die, having a second front surface, which is bonded to the first rear surface, and a second rear surface, and comprising a photodetector receiver analog circuit coupled to the at least one avalanche photodetector and an emitter driver circuit configured to drive a pulsed optical emitter; and
a third semiconductor die, having a third front surface, which is bonded to the second rear surface, and a third rear surface, and comprising logic circuits coupled to control the photodetector receiver analog circuit and the emitter driver circuit and to receive and process the electrical pulses output by the at least one avalanche photodetector.
2. The device according to claim 1 , wherein the first, second, and third semiconductor dies comprise silicon dies.
3. The device according to claim 2 , and comprising a III-V semiconductor die, having fourth front and rear surfaces, and comprising the optical emitter, which is coupled to be driven by the emitter driver circuit and is configured to output optical pulses through the fourth front surface.
4. The device according to claim 3 , wherein the optical emitter comprises a vertical-cavity surface-emitting laser (VCSEL).
5. The device according to claim 3 , wherein the first semiconductor die comprises first electrical contacts on the first front surface, and wherein the III-V semiconductor die is mounted on the first front surface and comprises second electrical contacts, which are connected to the first electrical contacts.
6. The device according to claim 3 , and comprising a carrier substrate, wherein the III-V semiconductor die and the third semiconductor die are both mounted on the carrier substrate.
7. The device according to claim 1 , wherein the at least one avalanche photodetector comprises a single-photon avalanche detector (SPAD).
8. The device according to claim 1 , wherein the at least one avalanche photodetector comprises an array of multiple photodetectors.
9. The device according to claim 1 , wherein the first rear surface is bonded to the second front surface by an oxide bond.
10. The device according to claim 9 , wherein the second rear surface and the third front surface comprise respective metal pads and are bonded together by hybrid bonding between the respective metal pads.
11. The device according to claim 1 , wherein the logic circuits in the third semiconductor die comprise complementary metal-oxide-semiconductor (CMOS) logic, while the emitter driver circuit in the second semiconductor die comprises n-type metal-oxide-semiconductor (NMOS) transistors or p-type metal-oxide-semiconductor (PMOS) transistors.
12. The device according to claim 1 , wherein the first semiconductor die comprises a metal layer, which is disposed between the at least one avalanche photodetector and the first rear surface and shields the photodetector receiver analog circuit from the incident photons.
13. A method for fabricating an optoelectronic device, the method comprising:
forming in a first semiconductor die at least one avalanche photodetector, which is configured to output electrical pulses in response to photons incident on a first front surface of the first semiconductor die;
bonding a second front surface of a second semiconductor die to a first rear surface of the first semiconductor die;
forming in the second semiconductor die a photodetector receiver analog circuit coupled to the at least one avalanche photodetector and an emitter driver circuit, which is configured to drive a pulsed optical emitter;
forming logic circuits in a third semiconductor die; and
bonding a third front surface of the third semiconductor die to a second rear surface of the second semiconductor die so as to couple the logic circuits to control the photodetector receiver analog circuit and the emitter driver circuit and to receive and process the electrical pulses output by the at least one avalanche photodetector.
14. The method according to claim 13 , wherein the first, second, and third semiconductor dies comprise silicon dies.
15. The method according to claim 14 , and comprising coupling a III-V semiconductor die, having fourth front and rear surfaces and comprising the optical emitter, to be driven by the emitter driver circuit so as to output optical pulses through the fourth front surface.
16. The method according to claim 13 , wherein the at least one avalanche photodetector comprises one or more single-photon avalanche detectors (SPADs).
17. The method according to claim 13 , wherein bonding the second front surface of the second semiconductor die to the first rear surface of the first semiconductor die comprises forming an oxide bond between the first rear surface and the second front surface.
18. The method according to claim 17 , wherein bonding the third front surface of the third semiconductor die to the second rear surface of the second semiconductor die comprises forming respective metal pads on the second and third semiconductor dies, and bonding the third front surface to the second rear surface by hybrid bonding between the respective metal pads.
19. The method according to claim 13 , wherein the logic circuits in the third die comprise complementary metal-oxide-semiconductor (CMOS) logic, while the drive circuits in the second die comprise n-type metal-oxide-semiconductor (NMOS) transistors or p-type metal-oxide-semiconductor (PMOS) transistors.
20. The method according to claim 13 , and comprising depositing a metal layer on the first semiconductor die, so that the metal layer is disposed between the at least one avalanche photodetector and the first rear surface and shields the photodetector receiver analog circuit from the incident photons.