Manufacturing method for semiconductor structures
The present disclosure provides a manufacturing method for semiconductor structures. The method includes the following operations: receiving a wafer having a plurality of dies; respectively forming a plurality of semiconductor structures in a plurality of banks in each of the plurality of dies, wherein each of the semiconductor structure includes a first fin array and a second fin array disposed above the first fin array; performing a PWG measurement on the wafer to obtain a displacement between a first fin of the first fin array and a first fin of the second fin array; and according to the displacement, determining a status of wafer.
1. A method for manufacturing and measuring a plurality of semiconductor structures, comprising:
receiving a wafer having a plurality of dies;
respectively forming the plurality of semiconductor structures in a plurality of banks in each of the plurality of dies, wherein each of the semiconductor structure includes a first fin array and a second fin array disposed above the first fin array, wherein the first fin array has a plurality of fins including a first fin to a Nth fin spaced apart from each other, and the second fin array has a plurality of fins including a first fin to a Nth fin spaced apart from each other, wherein the fins of the first fin array are aligned with the fins of the second fin array respectively when the second fin array overlaps on the first fin array;
when top portions of the first fin and the Nth fin of the first fin array are tilted away therefrom, performing a patterned wafer geometry (PWG) measurement on the wafer to obtain a displacement between the first fin of the first fin array and the first fin of the second fin array by the PWG in nanometer level, and to obtain a displacement between the Nth fin of the first fin array and the Nth fin of the second fin array by the PWG in nanometer level; and
after performing the PWG measurement, according to the displacement, determining a status of the wafer;
wherein when the displacement obtained according to the PWG measurement results is greater than a threshold value, the status of the wafer is determined as a fail status, and when the displacement obtained according to the PWG measurement results is not greater than the threshold value, the status of the wafer is determined as a pass status; when the status of the wafer is the fail status, removing the wafer from a batch of wafers, when the status of the wafer is the pass status, remaining the wafer in the batch of wafers.
2. The method of claim 1 , wherein respectively forming the plurality of semiconductor structures in the plurality of banks in each of the plurality of dies comprises:
forming the first fin array in each of the plurality of banks; and
forming the second fin array on the first fin array.
3. The method of claim 2 ,
wherein the first fin of the first fin array corresponds to the first fin of the second fin array, wherein the displacement between the first fin of the first fin array and the first fin of the second fin array is defined from a top view of the semiconductor structure and the displacement is determined to a misalignment between the top portion of the first fin of the first fin array and the first fin of the second fin array.
4. The method of claim 3 , wherein forming the first fin array in each of the plurality of banks comprises:
forming a first layer;
etching the first layer to form the first fin array; and
planarizing the first layer to expose a top surface of the first fin array.
5. The method of claim 4 , wherein forming the second fin array on the first fin array comprises:
forming a second layer on the first fin array;
etching the second layer to form the second fin array; and
planarizing the second layer to expose a top surface of the second fin array.
6. The method of claim 1 , wherein the threshold value is 1.5 nm.
7. The method of claim 5 , wherein performing the PWG measurement to obtain the displacement between the first fin of the first fin array and the first fin of the second fin array comprises:
obtaining a first overlap ratio of the first fin of the first fin array and the first fin of the second fin array;
obtaining a second overlap ratio of an Nth fin of the first fin array and an Nth fin of the second fin array;
obtaining a center overlap ratio of an Ath fin of the first fin array and an Ath fin of the second fin array; and
obtaining the displace according the first overlap ratio, the second overlap ratio, and the center overlap ratio,
wherein when N is an odd number, A is equal to (N+1)/2, and when N is an even number, A is equal to N/2,
wherein the center overlap ratio is zero, such that a top portion of the Ath fin of the first fin array is aligned with the Ath fin of the second fin array.
8. The method of claim 7 , wherein converting PWG measurement results of the first overlap ratio, the second overlap ratio, and the center overlap ratio to obtain the displacement comprises:
subtracting the first overlap ratio from the center overlap ratio to obtain a first magnification;
subtracting the second overlap ratio from the center overlap ratio to obtain a second magnification; and
obtaining the displacement according to the first magnification and the second magnification.
9. The method of claim 7 , wherein the first overlap ration is equal to the second overlap ratio.
10. The method of claim 8 , wherein the first magnification is equal to the second magnification.
11. The method of claim 8 , wherein obtaining the displacement according to the first magnification and the second magnification comprises:
obtaining an average magnification by averaging the first magnification and the second magnification; and
obtaining the displacement in a lookup table, wherein the lookup table is configured to store a correspondence of the displacement and the average magnification.