Rate matching methods for LDPC codes
A method of producing a set of coded bits from a set of information bits for transmission between a first node and a second node in a wireless communications system, the method comprises generating a codeword vector by encoding the set of information bits with a low-density parity-check code, wherein the codeword vector is composed of systematic bits and parity bits. The method comprises performing circular buffer-based rate matching on the generated codeword vector to produce the coded bits for transmission, wherein the circular buffer-based rate matching comprises puncturing a first plurality of systematic bits.
1. A method of producing a set of coded bits from a set of information bits for transmission between a wireless device and a network node in a wireless communications system, the method comprising:
generating a codeword vector with the set of information bits;
puncturing a portion of the information bits from the codeword vector before writing the codeword vector into a circular buffer, where the amount of bits in the punctured portion is twice a lifting factor of the parity check matrix and wherein columns in the parity check matrix that are mapped to the punctured information bits have a higher column weight than columns in the parity check matrix that are mapped to non-punctured bits; and
performing circular buffer-based rate matching to produce the coded bits for transmission,
wherein generating a codeword vector comprises:
attaching dummy bits to the set of information bits to make an information vector, and
encoding the information vector with a quasi-cyclic low-density parity-check code (QC-LDPC) that is specified through a parity check matrix to generate the codeword vector, wherein the QC-LDPC code is designed with the knowledge that the portion of information bits will be punctured, and
wherein performing circular buffer-based rate matching on the generated codeword vector to produce the coded bits for transmission comprises removing the attached dummy bits.
2. The method of claim 1 , wherein the portion of the information bits that are punctured precedes other information bits that are not punctured.
3. The method of claim 1 , wherein a plurality of redundancy versions are defined over the circular buffer such that coded bits for a retransmission are read from the circular buffer according to a corresponding redundancy version defined for the retransmission.
4. The method of claim 1 , wherein performing circular buffer-based rate matching to produce the coded bits for transmission comprises:
if a number of bits of the coded bits for transmission is larger than the total number of bits in the circular buffer, repeating one or more bits in the circular buffer by wrapping around.
5. The method of claim 1 , wherein removing the attached dummy bits comprises skipping the attached dummy bits when performing circular buffer-based rate matching.
6. The method of claim 1 , wherein performing circular buffer-based rate matching comprises implementing a channel interleaver on the punctured codeword vector.
7. A wireless device for producing a set of coded bits from a set of information bits for transmission to a network node in a wireless communications system, the wireless device comprising:
processing circuitry, the processing circuitry configured to:
generate a codeword vector with the set of information bits;
puncture a portion of the information bits from the codeword vector before writing the codeword vector into a circular buffer, where the amount of bits in the punctured portion is twice a lifting factor of the parity check matrix and wherein columns in the parity check matrix that are mapped to the punctured information bits have a higher column weight than columns in the parity check matrix that are mapped to non-punctured bits; and
perform circular buffer-based rate matching to produce the coded bits for transmission,
wherein, when generating the codeword vector, the processing circuitry is further configured to:
attach dummy bits to the set of information bits to make an information vector, and
encode the information vector with a quasi-cyclic low-density parity-check code (QC-LDPC) that is specified through a parity check matrix to generate the codeword vector, wherein the QC-LDPC code is designed with the knowledge that the portion of information bits will be punctured, and
wherein, when performing circular buffer-based rate matching, the processing circuitry is further configured to remove the attached dummy bits.
8. The wireless device of claim 7 , wherein the portion of the information bits that are punctured precedes other information bits that are not punctured.
9. The wireless device of claim 7 , wherein a plurality of redundancy versions are defined over the circular buffer such that coded bits for a retransmission are read from the circular buffer according to a corresponding redundancy version defined for the retransmission.
10. The wireless device of claim 7 , wherein the processing circuitry configured to perform circular buffer-based rate matching to produce the coded bits for transmission comprises processing circuitry configured to:
if a number of bits of the coded bits for transmission is larger than the total number of bits in the circular buffer, repeat one or more bits in the circular buffer by wrapping around.
11. The wireless device of claim 7 , wherein the processing circuitry configured to remove the attached dummy bits comprises processing circuitry configured to skip the attached dummy bits when performing circular buffer-based rate matching.
12. The wireless device of claim 7 , wherein the processing circuitry is configured to implement a channel interleaver on the punctured codeword vector as part of the circular buffer-based rate matching.
13. A network node for producing a set of coded bits from a set of information bits for transmission to a wireless device in a wireless communications system, the network node comprising:
processing circuitry, the processing circuitry configured to:
generate a codeword vector with the set of information bits;
puncture a portion of the information bits from the codeword vector before writing the codeword vector into a circular buffer, where the amount of bits in the punctured portion is twice a lifting factor of the parity check matrix and wherein columns in the parity check matrix that are mapped to the punctured information bits have a higher column weight than columns in the parity check matrix that are mapped to non-punctured bits; and
perform circular buffer-based rate matching to produce the coded bits for transmission,
wherein, when generating the codeword vector, the processing circuitry is further configured to:
attach dummy bits to the set of information bits to make an information vector, and
encode the information vector with a quasi-cyclic low-density parity-check code (QC-LDPC) that is specified through a parity check matrix to generate the codeword vector, wherein the QC-LDPC code is designed with the knowledge that the portion of information bits will be punctured, and
wherein, when performing circular buffer-based rate matching, the processing circuitry is further configured to remove the attached dummy bits.
14. The network node of claim 13 , wherein the portion of the information bits that are punctured precedes other information bits that are not punctured.
15. The network node of claim 13 , wherein a plurality of redundancy versions are defined over the circular buffer such that coded bits for a retransmission are read from the circular buffer according to a corresponding redundancy version defined for the retransmission.
16. The network node of claim 13 , wherein the processing circuitry configured to perform circular buffer-based rate matching to produce the coded bits for transmission comprises processing circuitry configured to:
if a number of bits of the coded bits for transmission is larger than the total number of bits in the circular buffer, repeat one or more bits in the circular buffer by wrapping around.
17. The network node of claim 13 , wherein the processing circuitry configured to remove the attached dummy bits comprises processing circuitry configured to skip the attached dummy bits when performing circular buffer-based rate matching.
18. The network node of claim 13 , wherein the processing circuitry is configured to implement a channel interleaver on the punctured codeword vector as part of the circular buffer-based rate matching.