FinFET structure with airgap and method of forming the same
Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin formed on a substrate; and a gate structure disposed over a channel region of the semiconductor fin, the gate structure including a gate dielectric layer and a gate electrode, wherein the gate dielectric layer includes a bottom portion and a side portion, and the gate electrode is separated from the side portion of the gate dielectric layer by a first air gap.
1. A device comprising:
an active region disposed on a substrate;
a gate structure disposed on the active region, the gate structure including:
a gate dielectric layer, and
a gate electrode disposed on the gate dielectric layer, wherein the gate electrode has a bottom surface interfacing with the gate dielectric layer and a sidewall surface that is spaced apart from a first side surface of the gate dielectric layer by a first air gap such that the sidewall surface of the gate electrode and the first side surface of the gate dielectric layer are exposed in the first air gap;
a gate spacer extending along a second side surface of the gate dielectric layer that faces away from the gate electrode; and
a protective layer disposed directly on top surfaces of the gate electrode and the gate dielectric layer.
2. The device of claim 1 ,
wherein a top surface of the protective layer is coplanar with top surfaces of the gate spacer and the gate dielectric layer.
3. The device of claim 2 , wherein the protective layer includes SiN doped with carbon.
4. The device of claim 2 , further comprising an etch stop layer disposed directly on the protective layer and the gate dielectric layer.
5. The device of claim 1 , wherein the gate dielectric layer extends to a greater height above the substrate than the gate electrode.
6. The device of claim 1 , further comprising:
a source/drain feature disposed on the active region;
an interlayer dielectric layer disposed on the substrate; and
a contact feature extending through the interlayer dielectric layer toward the source/drain feature such that the contact feature is electrically coupled to the source/drain feature, wherein the interlayer dielectric layer and the contact feature define a second airgap extending along the contact feature.
7. The device of claim 6 , further comprising a protective layer disposed along a sidewall of the contact feature, and
wherein the interlayer dielectric layer, the protective layer, the source/drain feature and the contact feature are exposed to the air gap.
8. The device of claim 7 , wherein the protective layer includes a material selected from the group consisting of SiGe, SiN and SiO.
9. A device comprising:
an active region disposed on a substrate;
a gate structure disposed on the active region, the gate structure including:
a gate dielectric layer, and
a gate electrode disposed on the gate dielectric layer;
a source/drain feature disposed on the active region;
a gate spacer disposed along a sidewall of the gate dielectric layer;
an interlayer dielectric (ILD) layer over the source/drain feature;
a contact feature extending through the ILD layer to electrically couple with the source/drain feature; and
a first air gap extending from the contact feature to the source/drain feature such that sidewalls of the contact feature are spaced apart from sidewalls of the ILD layer by the first air gap,
wherein top surfaces of the gate spacer and the ILD layer are coplanar.
10. The device of claim 9 , further comprising a second air gap extending from the gate electrode to the gate dielectric layer.
11. The device of claim 10 , wherein the second air gap extends to the same height above the substrate as the gate electrode.
12. The device of claim 10 , wherein the gate dielectric layer extends to a greater height above the substrate than the second air gap.
13. The device of claim 10 , wherein the first air gap extends to a greater height above the substrate than the second air gap.
14. The device of claim 9 , further comprising a first protective layer disposed along a sidewall of the contact feature, wherein a portion of the sidewall of the contact feature is not cover by the first protective layer and is exposed to the first air gap.
15. The device of claim 14 , further comprising:
a second protective layer disposed on the gate electrode, and
a second air gap extending from the gate electrode to the gate dielectric layer, wherein the second protective layer, the gate electrode and the gate dielectric layer are exposed to the second air gap.
16. A method comprising:
forming a source/drain feature on a substrate;
forming an interlayer dielectric layer on the substrate;
forming a first trench in the interlayer dielectric layer;
forming a gate dielectric layer in the first trench;
forming a first layer on the gate dielectric layer within the first trench;
forming a gate electrode on the first layer within the first trench;
forming a second trench in the interlayer dielectric layer to expose the source/drain feature;
forming a second layer on the source/drain feature within the second trench;
forming a conductive material within the second trench on the second layer; and
removing the first layer and the second layer such that a first air gap is formed between the gate electrode and the gate dielectric layer and a second air gap is formed between the conductive material and the interlayer dielectric layer.
17. The method of claim 16 , wherein forming the second layer on the source/drain feature within the second trench include forming the second layer directly on the gate electrode.
18. The method of claim 17 , further comprising forming a protective layer directly on the second layer prior to forming the conductive material within the second trench, and
wherein the protective layer is disposed along the conductive material after the removing of the first layer and the second layer.
19. The method of claim 16 , further comprising:
after the removing of the first layer and the second layer, recessing the gate electrode;
forming a protective layer directly on the recessed gate electrode, the protective layer being exposed to the first air gap.
20. The method of claim 19 , further comprising forming an etch stop layer that extends from over the protective layer to over the second air gap such that the second air gap is sealed by the forming of the etch stop layer, the etch stop layer being exposed to the second air gap after the forming of the etch stop layer.