Semiconductor structure
A semiconductor structure includes a first die and a plurality of first dummy pads. The first die includes a first interconnect structure and a first active pad electrically connected to the first interconnect structure. The first dummy pads laterally surround the first active pad and are electrically floating.
1. A semiconductor structure, comprising:
a first die, comprising a first interconnect structure and a first active pad electrically connected to the first interconnect structure; a first active bonding via, wherein the first active pad has a first surface facing the first interconnect structure and a second surface opposite to the first surface, the first active bonding via has a third surface facing the first interconnect structure and a fourth surface opposite to the third surface, and the second surface of the first active pad is disposed between the third surface and the fourth surface of the first active bonding via; and
a first bonding dielectric layer, covering the second surface of the first active pad and laterally encapsulating sidewalls of the first active pad and the first active bonding via, wherein the first bonding dielectric layer is a single layer.
2. The semiconductor structure according to claim 1 , wherein the first active bonding via is electrically connected to the first interconnect structure and electrically isolated from the first active pad.
3. The semiconductor structure according to claim 1 , further comprising a plurality of first dummy pads and a plurality of first dummy bonding vias connected to the first dummy pads respectively, wherein the first dummy pads laterally surround the first active pad and are electrically floating.
4. The semiconductor structure according to claim 3 , wherein a width of the first active bonding via is larger than a width of one of the first dummy bonding vias.
5. The semiconductor structure according to claim 3 , wherein the third surface of the first active bonding via is substantially coplanar with first surfaces of the first dummy bonding vias, and the fourth surface of the first active bonding via is substantially coplanar with second surfaces opposite to the first surfaces of the first dummy bonding vias.
6. The semiconductor structure according to claim 1 , wherein the first surface of the first active pad is substantially coplanar with a surface of the first bonding dielectric layer.
7. A semiconductor structure, comprising:
a first die, comprising a substrate, a first interconnect structure, a first active pad electrically connected to the first interconnect structure, a first active bonding via electrically connected to the first active pad, wherein the first interconnect structure is disposed between the substrate and the first active pad, and the first active pad is disposed between the first interconnect structure and the first active bonding via; and
a plurality of first dummy bonding pads surrounding the first active pad, wherein the first dummy bonding pads are electrically floating.
8. The semiconductor structure according to claim 7 , further comprising a first bonding dielectric layer over the first die, wherein the first active bonding via is disposed in the first bonding dielectric layer.
9. The semiconductor structure according to claim 7 , wherein the first active bonding via is in direct contact with the first active pad.
10. The semiconductor structure according to claim 7 , further comprising a plurality of first dummy bonding vias surrounding the first active bonding via, wherein the first dummy bonding vias are electrically floating.
11. The semiconductor structure according to claim 10 , wherein the first dummy bonding vias and the first active bonding via are disposed in a first bonding dielectric layer.
12. The semiconductor structure according to claim 7 , wherein a surface of the first active pad is substantially coplanar with surfaces of the first dummy bonding pads.
13. The semiconductor structure according to claim 7 , further comprising a plurality of first dummy bonding vias, wherein the first dummy bonding pads are respectively disposed between the first interconnect structure and the first dummy bonding vias.
14. A semiconductor structure, comprising:
a first die and a second die;
at least one first active bonding via and a plurality of first dummy bonding vias between the first die and the second die, wherein the first dummy bonding vias laterally surround the at least one first active bonding via and are electrically floating;
at least one first active pad electrically connected to the at least one first active bonding via; and
at least one second active bonding via bonded to the at least one first active bonding via, wherein the at least one first active bonding via is physically connected to the at least one first active pad, the at least one first active pad has a first width along a first direction, and the at least one first active bonding via has a second width smaller than the first width along the first direction.
15. The semiconductor structure according to claim 14 , further comprising a plurality of second dummy bonding vias between the first die and the second die, wherein the second dummy bonding vias are bonded to the first dummy bonding vias respectively.
16. The semiconductor structure according to claim 15 , wherein a width of the at least one second active bonding via is larger than a width of the second dummy bonding vias.
17. The semiconductor structure according to claim 14 , wherein a width of the at least one first active bonding via is substantially the same as a width of the at least one second active bonding via.
18. The semiconductor structure according to claim 14 , wherein a width of the at least one first active bonding via is larger than a width of the first dummy bonding vias.
19. The semiconductor structure according to claim 14 , wherein a surface of the at least one first active bonding via is substantially coplanar with surfaces of the first dummy bonding vias.
20. The semiconductor structure according to claim 14 , wherein the first die comprises at least one first conductive feature and a plurality of first dummy features electrically isolated from the at least one first conductive feature, the at least one first active bonding via is in direct contact with the at least one first conductive feature, and the first dummy bonding vias are in direct contact with the first dummy features respectively.