Semiconductor package structure
A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor component, a conductive pillar, and a second semiconductor component. The redistribution layer is over the substrate. The first semiconductor component is over the redistribution layer. The conductive pillar is adjacent to the first semiconductor component, wherein the first semiconductor component and the conductive pillar are surrounded by a molding material. The second semiconductor component is over the molding material, wherein the second semiconductor component is electrically coupled to the redistribution layer through the conductive pillar.
1. A semiconductor package structure, comprising:
a substrate;
a redistribution layer over the substrate and having a first surface and a second surface opposite to the first surface;
a plurality of first bump structures on the first surface of the redistribution layer and electrically coupling the redistribution layer to a wiring structure of the substrate;
a first semiconductor component on the first surface of the redistribution layer and adjacent to the plurality of first bump structures;
a first passivation layer on the first semiconductor component;
a plurality of first conductive vias in the first passivation layer and electrically coupled to the first semiconductor component;
a plurality of second bump structures between the redistribution layer and the first conductive vias and directly connecting the redistribution layer and the first conductive vias;
a second semiconductor component on the second surface of the redistribution layer; and
a first underfill material that surrounds the plurality of first bump structures, wherein the first underfill material is in direct contact with a top surface of a first portion of the substrate and exposes a top surface of a second portion of the substrate, wherein the top surface of the first portion of the substrate is substantially level with the top surface of the second portion of the substrate,
wherein the second semiconductor component is electrically coupled to the first semiconductor component through the redistribution layer, and is electrically coupled to the wiring structure of the substrate through the plurality of first bump structures.
2. The semiconductor package structure as claimed in claim 1 , wherein the first semiconductor component is electrically coupled to the redistribution layer through the plurality of second bump structures.
3. The semiconductor package structure as claimed in claim 1 , wherein the first underfill material surrounds the plurality of second bump structures.
4. The semiconductor package structure as claimed in claim 1 , wherein the first underfill material covers sidewalls of the first semiconductor component.
5. The semiconductor package structure as claimed in claim 1 , wherein the plurality of first bump structures have a height greater than a height of the first semiconductor component.
6. The semiconductor package structure as claimed in claim 1 , wherein the redistribution layer laterally extends beyond sidewalls of the first semiconductor component.
7. The semiconductor package structure as claimed in claim 1 , further comprising a second underfill material on the first passivation layer and surrounded by the first underfill material.
8. The semiconductor package structure as claimed in claim 1 , wherein the first underfill material extends continuously from above the first surface of the redistribution layer to a top surface of the substrate.
9. The semiconductor package structure as claimed in claim 1 , further comprising:
a second passivation layer on the second semiconductor component; and
a plurality of second conductive vias in the second passivation layer and electrically coupled to the redistribution layer.
10. The semiconductor package structure as claimed in claim 9 , wherein the second passivation layer and the plurality of second conductive vias are in direct contact with the redistribution layer.
11. The semiconductor package structure as claimed in claim 9 , wherein a sidewall of the second passivation layer is coplanar with a sidewall of the redistribution layer.
12. The semiconductor package structure as claimed in claim 9 , wherein a sidewall of the second semiconductor component is coplanar with a sidewall of the redistribution layer.
13. The semiconductor package structure as claimed in claim 1 , wherein a height of the plurality of first bump structures is substantially equal to a total height of the first semiconductor component, one of the plurality of first conductive vias, and one of the plurality of second bump structures.
14. The semiconductor package structure as claimed in claim 1 , further comprising:
conductive terminals below the substrate,
wherein the conductive terminals are in direct contact with a bottom surface of the first portion of the substrate and a bottom surface of the second portion of the substrate.