Victim cache that supports draining write-miss entries
A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.
1. A device, comprising:
a processor;
a cache memory including:
a cache line configured to store an entry; and
a line type entry configured to store a value indicating whether the entry stored in the cache line is a write-miss entry or an entry evicted from another cache memory;
an interface configured to couple the cache memory with the processor; and
a controller configured to:
determine whether the interface is in a state; and
based on a determination that the interface is in the state, evict the entry from the cache line based on the value of the line type entry indicating that the entry stored in the cache line is a write-miss entry.
2. The device of claim 1 , further comprising a tag RAM, wherein the controller is configured to evict the cache line based on the tag RAM.
3. The device of claim 1 , wherein the controller is configured to evict the cache line based on a first-in-first-out policy.
4. The device of claim 1 , wherein the controller is configured to evict the cache line based on a least recently used policy.
5. The device of claim 1 , wherein the controller is configured to evict the cache line based on a random selection policy.
6. The device of claim 1 , further comprising a drain buffer, wherein the controller is configured to evict the cache line by moving a packet from the cache line to the drain buffer until an acknowledgment is received.
7. The device of claim 6 , further comprising an additional cache memory, wherein the controller is further configured to move the packet from the drain buffer to the additional cache memory, and wherein the additional cache memory is configured to provide the acknowledgment.
8. The device of claim 1 , wherein
the cache memory is a victim cache memory.
9. The device of claim 1 , wherein the state is an idle state.
10. The device of claim 9 , wherein to determine whether the interface is in the state, the controller is configured to determine whether the interface has been in the idle state for a specific number of clock cycles.
11. A method, comprising:
storing data in a cache line of a cache memory;
storing a value in a line type entry of the cache memory that indicates whether the data is associated with a write-miss entry or an entry evicted from another cache memory;
detecting a state of an interface of the cache memory; and
based on detecting the state, evicting the data from the cache line based on the value indicating that the data is associated with a write-miss entry.
12. The method of claim 11 , wherein evicting the data comprises evicting the data based on walking a set of tag RAM entries.
13. The method of claim 11 , wherein evicting the data comprises evicting the data based on a first-in-first-out policy.
14. The method of claim 11 , wherein evicting the data comprises evicting the data based on a least recently used policy.
15. The method of claim 11 , wherein evicting the data comprises evicting the data based on a random replacement policy.
16. The method of claim 11 , wherein evicting the data comprises moving the data from the cache line to a drain buffer of the cache memory until receiving an acknowledgement.
17. The method of claim 16 , wherein evicting the data further comprises moving the data from the drain buffer to an additional cache memory, and the method further comprises receiving the acknowledgement from the additional cache memory.
18. The method of claim 11 , wherein the cache memory is a victim cache memory.
19. The method of claim 11 , wherein the state is an idle state.
20. The method of claim 19 , wherein detecting the state of the interface comprises detecting that the interface has been in the idle state for a specific number of clock cycles.