Integrated circuit having contact jumper
An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.
1. An integrated circuit comprising:
first and second fins each extending in a first direction;
first and second gate lines each extending longitudinally across the first and second fins in a second direction substantially perpendicular to the first direction; and
a first contact jumper comprising:
a first power rail, to which a first power supply voltage is applied, extending in the first direction, and
a first conductive pattern extending longitudinally in the second direction and connected to the first power rail.
2. The integrated circuit of claim 1 , wherein the first conductive pattern is located above the first fin and extends between the first and second gate lines.
3. The integrated circuit of claim 1 , wherein the first conductive pattern corresponds to a first source/drain contact.
4. The integrated circuit of claim 3 , wherein the first source/drain contact is connected to a first transistor including the first gate line and a second transistor including the second gate line.
5. The integrated circuit of claim 1 , wherein the first power supply voltage corresponds to a power supply voltage or a ground voltage.
6. The integrated circuit of claim 1 , wherein the first power rail and the first conductive pattern are implemented by first contacts.
7. The integrated circuit of claim 1 , upper surfaces of the first power rail and the first conductive pattern are substantially coplanar at a level above a substrate.
8. The integrated circuit of claim 1 , further comprising a second contact jumper spaced apart from the first contact jumper.
9. The integrated circuit of claim 8 , wherein the second contact jumper comprises:
a second power rail, to which a second power supply voltage is applied, extending in the first direction, and
a second conductive pattern extending longitudinally in the second direction and connected to the second power rail.
10. The integrated circuit of claim 9 , wherein the second conductive pattern is located above the second fin and extends between the first and second gate lines.
11. The integrated circuit of claim 9 , wherein the second conductive pattern corresponds to a second source/drain contact.
12. The integrated circuit of claim 11 , wherein the second source/drain contact is connected to a third transistor including the first gate line and a fourth transistor including the second gate line.
13. The integrated circuit of claim 9 , further comprising:
third gate line extending longitudinally across the first and second fins in the second direction,
wherein the second conductive pattern is located above the second fin and extends between the first and third gate lines.
14. The integrated circuit of claim 9 , wherein the second power supply voltage corresponds to a ground voltage or a power supply voltage.
15. The integrated circuit of claim 9 , upper surfaces of the second power rail and the second conductive pattern are substantially coplanar at a level above a substrate.
16. The integrated circuit of claim 1 , wherein the first power rail is physically separated from the first and second gate lines.
17. The integrated circuit of claim 1 , wherein the first power rail is arranged on a shallow trench isolation in a substrate.
18. The integrated circuit of claim 1 , further comprising:
a via on the first contact jumper; and
a metal layer arranged on the via and electrically connected to the first contact jumper.
19. The integrated circuit of claim 1 , wherein the first and second fins are spaced in the second direction such that a middle region exists as interposed between the first and second fins in the second direction.
20. The integrated circuit of claim 1 , wherein the first conductive pattern is electrically insulated from the first and second gate lines.
21. An integrated circuit comprising:
first and second fins each extending in a first direction;
a plurality of gate lines each extending longitudinally across the first and second fins in a second direction substantially perpendicular to the first direction;
a via jumper comprising a first conductive pattern extending in the first direction and a second conductive pattern extending longitudinally in the second direction and connected to the first conductive pattern; and
a metal layer arranged above the via jumper.
22. The integrated circuit of claim 21 , wherein the metal layer comprises:
a first metal pattern connecting to the first conductive pattern, and
a second metal pattern connecting to the second conductive pattern.
23. The integrated circuit of claim 21 , wherein the first and second fins are spaced in the second direction such that a middle region exists as interposed between the first and second fins in the second direction,
wherein the metal layer comprises:
a first metal pattern extending in the first direction above the first fin,
a second metal pattern extending in the first direction above the second fin, and
a third metal pattern extending in the second direction in the middle region.
24. The integrated circuit of claim 23 , wherein the plurality of gate lines comprises a first gate line, a second gate line, and a third gate line,
wherein the integrated circuit further comprises:
a first contact above the first fin, the first contact extending between the first and second gate lines;
a second contact above the first fin, the second contact extending between the second and third gate lines; and
a third contact on the second gate line,
wherein the first conductive pattern is located above the first and second contacts and below the first metal pattern, and
wherein the second conductive pattern is located on the third contact and below the third metal pattern.
25. The integrated circuit of claim 23 , wherein the plurality of gate lines comprises a first gate line and a second gate line,
wherein the integrated circuit further comprises:
a first contact above the first fin, the first contact extending between the first and second gate lines;
a second contact on the first gate line; and
a third contact on the second gate line, and
wherein the first conductive pattern is located above the second and third contacts and below the third metal pattern, and
wherein the second conductive pattern is located on the first contact and below the first metal pattern.
26. An integrated circuit comprising:
first and second fins each extending in a first direction;
a plurality of gate lines each extending longitudinally across the first and second fins in a second direction substantially perpendicular to the first direction;
a via jumper comprising a first conductive pattern extending in the first direction and a second conductive pattern extending longitudinally in the second direction and connected to the first conductive pattern;
a first metal layer arranged below the via jumper; and
a second metal layer arranged above the via jumper.
27. The integrated circuit of claim 26 , wherein the first metal layer comprises:
a first metal pattern connecting to the first conductive pattern, and
a second metal pattern connecting to the second conductive pattern.
28. The integrated circuit of claim 26 , wherein the first and second fins are spaced in the second direction such that a middle region exists as interposed between the first and second fins in the second direction, and
wherein the first metal layer comprises:
a first metal pattern extending in the first direction above the first fin,
a second metal pattern extending in the first direction above the second fin, and
a plurality of third metal patterns extending in the second direction in the middle region.
29. The integrated circuit of claim 28 , wherein the first conductive pattern is located above at least two of the plurality of third metal patterns and below the second metal layer, and
wherein the second conductive pattern is located on the first metal pattern and below the second metal layer.
30. The integrated circuit of claim 28 , wherein the first conductive pattern is located above at least two of the plurality of third metal patterns and below the second metal layer, and
wherein the second conductive pattern is located on the second metal pattern and below the second metal layer.