Semiconductor package and method for manufacturing semiconductor package
A semiconductor package includes a first redistribution structure, including a first insulating layer and a first redistribution layer disposed below the first insulating layer; a semiconductor chip disposed on the first redistribution structure, including a connection terminal electrically connected to the first redistribution layer and buried in the first insulating layer; an encapsulant disposed on the first redistribution structure that seals a portion of the semiconductor chip; a second redistribution structure, including a second redistribution layer disposed on the encapsulant; and a through via, including a pattern portion buried in the first insulating layer and electrically connected to the first redistribution layer and a via portion penetrating through the encapsulant and electrically connecting the pattern portion and the second redistribution layer. The connection terminal and the pattern portion are located at a first level and are electrically connected to each other at a second level lower than the first level.
1. A method of manufacturing semiconductor package, comprising:
forming an encapsulant structure that includes a semiconductor chip that includes a connection terminal and an encapsulant that seals the semiconductor chip, wherein the encapsulant structure includes a front side from which the connection terminal protrudes and a back side opposite to the front side;
forming a through-hole that penetrates through the encapsulant from the front side to the back side;
forming a seed layer that extends along an inner wall of the through-hole and the front side of the encapsulant structure;
forming a through via that includes a via portion in the through-hole and a pattern portion that protrudes on the front side of the encapsulant structure;
removing a portion of the seed layer exposed by the pattern portion of the through via;
forming a front redistribution structure from the front side of the encapsulant structure, wherein the front redistribution structure includes a front insulating layer that covers the connection terminal and the pattern portion, front redistribution layers on the front insulating layer, and frontside vias that penetrate through the front insulating layer and electrically connect the front redistribution layers to the connection terminal and the pattern portion of the through via; and
forming a back redistribution structure on the back side of the encapsulant structure, wherein the back redistribution structure includes a back insulating layer, back redistribution layers on the back insulating layer, and backside vias that penetrate through the back insulating layer and electrically connect the back redistribution layers to the via portion of the through via,
wherein a lower surface of the connection terminal is located at a first level, and a lower surface of the pattern portion is located at a second level lower than the first level.
2. The method of manufacturing semiconductor package according to claim 1 , wherein the via portion has a tapered shape toward the back side of the encapsulant structure.
3. The method of manufacturing semiconductor package according to claim 1 , wherein the frontside vias are in contact with the lower surface of the connection terminal, and the lower surface of the pattern portion of the through via.
4. The method of manufacturing semiconductor package according to claim 1 , wherein the frontside vias comprise
a first frontside via that electrically connects the front redistribution layers to the connection terminal, and
a second frontside via that electrically connects the front redistribution layers to the pattern portion of the through via, wherein
a height of the first frontside via is greater than a height of the second frontside via.
5. The method of manufacturing semiconductor package according to claim 1 , wherein the backside vias comprise a first backside via in contact with an upper surface of the via portion of the through via.
6. The method of manufacturing semiconductor package according to claim 5 , wherein the upper surface of the via portion is coplanar with the back side of the encapsulant structure.
7. The method of manufacturing semiconductor package according to claim 1 , further comprising, before forming the back redistribution structure,
patterning a metal layer attached to the back side of the encapsulant structure,
wherein the patterned metal layer is covered by the back insulating layer.
8. The method of manufacturing semiconductor package according to claim 7 , wherein the backside vias comprise
a first backside via in contact with an upper surface of the via portion of the through via, and
a second backside via in contact with an upper surface of the patterned metal layer.
9. The method of manufacturing semiconductor package according to claim 8 , wherein a height of the first backside via is greater than a height of the second backside via.
10. The method of manufacturing semiconductor package according to claim 1 ,
wherein the connection terminal includes a first side surface,
wherein the pattern portion includes a second side surface that faces the first side surface of the connection terminal in a first direction, and
wherein the front insulating layer fills between the first side surface and the second side surface in the first direction.
11. The method of manufacturing semiconductor package according to claim 1 , wherein the through via has an integrated structure in which a boundary between the pattern portion and the via portion is not distinguishable.
12. The method of manufacturing semiconductor package according to claim 1 , wherein at least a portion of an upper surface of the pattern portion is in contact with the encapsulant.
13. He method of manufacturing semiconductor package according to claim 12 , wherein the seed layer is disposed between the upper surface of the pattern portion and the encapsulant.
14. A method of manufacturing semiconductor package, comprising:
forming an encapsulant structure that has a front surface from which a connection terminal protrudes and a back surface opposite to the front surface, wherein the encapsulant structure includes a semiconductor chip that has a front side on which the connection terminal is disposed, and an encapsulant that covers a back side of the semiconductor chip and a lateral side of the semiconductor chip, wherein the front side of the semiconductor chip provides the front surface of the encapsulant structure;
forming a through-hole that penetrates through the encapsulant from the front surface to the back surface, wherein the through-hole has a tapered shape toward the back surface of the encapsulant structure;
forming a through via that includes a via portion in the through-hole and a pattern portion disposed on the front surface of the encapsulant structure, wherein the pattern portion extends along the front surface to overlap the connection terminal in a lateral direction parallel to the front surface, and is electrically insulated from the semiconductor chip and the connection terminal;
forming a front redistribution structure on the front surface of the encapsulant structure, wherein the forming of the front redistribution structure comprises, forming front redistribution layers, and frontside vias that electrically connect the pattern portion of the through via to the semiconductor chip and the connection terminal; and
forming a back redistribution structure on the back surface of the encapsulant structure, wherein the back redistribution structure includes back redistribution layers, and backside vias electrically that connect the back redistribution layers to the via portion of the through via.
15. The method of manufacturing semiconductor package according to claim 14 , wherein the frontside vias comprise
a first frontside via connected to the connection terminal, and
a second frontside via connected to the pattern portion of the through via, wherein
a height of the first frontside via is greater than a height of the second frontside via.
16. A method of manufacturing semiconductor package, comprising:
forming an encapsulant structure that has a front surface from which a connection terminal protrudes and a back surface opposite to the front surface, wherein the encapsulant structure includes a semiconductor chip that has a front side on which the connection terminal is disposed, and an encapsulant that covers a back side of the semiconductor chip and a lateral side of the semiconductor chip, wherein the front side of the semiconductor chip provides the front surface of the encapsulant structure;
forming a through-hole that penetrates through the encapsulant from the front surface to the back surface;
forming a through via that includes a via portion in the through-hole and a pattern portion disposed on the front surface of the encapsulant structure, wherein the pattern portion extends along the front surface to overlap the connection terminal in a lateral direction parallel to the front surface, and is electrically insulated from the semiconductor chip and the connection terminal;
forming a front redistribution structure on the front surface of the encapsulant structure,
wherein the forming of the front redistribution structure comprises forming front redistribution layers, and frontside vias that electrically connect pattern portion of the through via to the semiconductor chip and the connection terminal;
forming a metal layer on the back surface of the encapsulant structure; and
forming a back redistribution structure on the back surface of the encapsulant structure, wherein the back redistribution structure includes back redistribution layers, and backside vias that electrically connect the back redistribution layers to the via portion of the through via and the metal layer.
17. The method of manufacturing semiconductor package according to claim 16 , wherein the backside vias comprise
a first backside via connected to the via portion of the through via, and
a second backside via connected to the metal layer.
18. The method of manufacturing semiconductor package according to claim 17 , wherein a height of the first backside via is greater than a height of the second backside via.
19. The method of manufacturing semiconductor package according to claim 16 , wherein a height from the front surface of the encapsulant structure to a lower surface of the connection terminal is lower than a height from the front surface of the encapsulant structure to a lower surface of the pattern portion of the through via.