Metal gate structures of semiconductor devices
View Patent ↗A method of fabricating a semiconductor device includes forming first and second nanostructured layers arranged in an alternating configuration on a substrate, forming first and second nanostructured channel regions in the first nanostructured layers, forming first and second gate-all-around structures wrapped around each of the first and second nanostructured channel regions. The forming the GAA structures includes depositing first and second gate barrier layers having similar material compositions and work function values on the first and second gate dielectric layers, forming first and second diffusion barrier layers on the first and second gate barrier layers, and doping the first and second gate barrier layers from a dopant source layer through the first and second diffusion barrier layers. The first diffusion barrier layer is thicker than the second diffusion barrier layer and the doped first and second gate barrier layers have work function values and doping concentrations different from each other.
1 . A device, comprising:
first and second stacks of first and second nanostructured layers arranged in an alternating configuration on a substrate;
first and second epitaxial regions of opposite conductivity type on the first and second stacks, respectively;
first and second nanostructured channel regions in the first nanostructured layers of the first and second stacks, respectively; and
first and second gate-all-around (GAA) structures wrapped around each of the first and second nanostructured channel regions, respectively, wherein the first and second GAA structures comprise:
first and second gate dielectric layers wrapped around the first and second nanostructured channel regions, respectively;
first and second gate barrier layers disposed on the first and second gate dielectric layers, respectively, the first and second gate barrier layers having similar material compositions and different work function values and doping concentrations from one another; and
first and second diffusion barrier layers on the first and second gate barrier layers, respectively, the first diffusion barrier layer being thicker than the second diffusion barrier layer.
2 . The device of claim 1 , wherein the first and second gate barrier layers comprise a first layer of diffusion barrier material.
3 . The device of claim 1 , further comprising a nucleation layer on the first and second diffusion barrier layers.
4 . The device of claim 3 , further comprising a dopant source layer on the nucleation layer.
5 . The device of claim 4 , further comprising a nitride capping layer on the dopant source layer.
6 . The device of claim 1 , the first and second GAA structures further comprising:
a first gate structure between adjacent first epitaxial regions;
a second gate structure between adjacent second epitaxial regions;
first and second gate barrier layers within the first and second gate structures, respectively; and
first and second diffusion barrier layers within the first and second gate structures on the first and second gate barrier layers, respectively.
7 . The device of claim 6 , the first and second GAA structures further comprising:
a third gate structure between adjacent first nanostructured channel regions;
a fourth gate structure between adjacent second nanostructured channel regions;
first and second gate barrier layers within the third and fourth gate structures, respectively; and
first and second diffusion barrier layers within the third and fourth gate structures, respectively, on the first and second gate barrier layers.
8 . The device of claim 1 , the first and second GAA structures further comprising:
a first gate structure between adjacent first nanostructured channel regions;
a second gate structure between adjacent second nanostructured channel regions; and
first and second diffusion barrier layers within the first and second gate structures on the first and second gate barrier layers, respectively.
9 . A semiconductor device, comprising:
a substrate;
an epitaxial region on the substrate;
a nanostructured channel region on the substrate;
a dielectric stack, surrounding the nanostructured channel region, comprising:
an oxide layer;
an interfacial oxide layer comprising hafnium silicate (HfSiO x ) disposed on the oxide layer;
a gate dielectric layer disposed on the interfacial oxide layer;
an oxide capping layer comprising hafnium titanium silicate (HfTiSiO x ) disposed on the gate dielectric layer; and
a gate barrier layer comprising a conductive material disposed on the dielectric stack;
a gate work function layer disposed on the gate barrier layer; and
a gate metal fill layer disposed on the gate work function layer.
10 . The semiconductor device of claim 9 , wherein the gate barrier layer comprises tungsten or cobalt dopants.
11 . The semiconductor device of claim 9 , wherein the gate barrier layer comprises a metal layer or a metal nitride layer.
12 . The semiconductor device of claim 9 , wherein the oxide capping layer comprises a metal oxide layer and the oxide layer comprises a non-metal oxide layer.
13 . The semiconductor device of claim 9 , wherein the gate barrier layer comprises a work function value in a range of about 4.4 eV to about 4.8 eV.
14 . The semiconductor device of claim 9 , wherein the gate work function layer comprises metal or non-metal dopants.
15 . A semiconductor device, comprising:
first and second stacks of first and second nanostructured layers arranged in an alternating configuration on a substrate;
first and second nanostructured channel regions in the first nanostructured layers of the first and second stacks, respectively;
first and second gate-all-around (GAA) structures wrapped around each of the first and second nanostructured channel regions, respectively, wherein the first and second GAA structures comprise:
first and second high-k gate dielectric layers wrapped around the first and second nanostructured channel regions, respectively;
first and second oxide capping layers on the first and second high-k gate dielectric layers, respectively; and
first and second gate barrier layers disposed on the first and second oxide capping layers wrapped around the first and second nanostructured channel regions, respectively, wherein the first and second gate barrier layers comprise conductive materials and non-metal dopants; and
first and second oxide layers disposed between the first nanostructured channel region and the first high-k gate dielectric layer, wherein the first oxide layer comprises a non-metal oxide layer and the second oxide layer comprises a metal oxide layer.
16 . The semiconductor device of claim 15 , wherein the first and second GAA structures further comprise first and second gate work function layers disposed on the first and second gate barrier layers, respectively, and wherein the first and second gate work function layers comprise work function values and doping concentrations different from each other.
17 . The semiconductor device of claim 15 , further comprising first and second epitaxial regions of opposite conductivity disposed on the first and second stacks, respectively.
18 . The semiconductor device of claim 15 , further comprising first and second epitaxial regions of a same conductivity disposed on the first and second stacks, respectively.
19 . The semiconductor device of claim 15 , further comprising an oxide layer disposed between the first nanostructured channel region and the first high-k gate dielectric layer.
20 . The semiconductor device of claim 15 , wherein the non-metal dopants of the first gate barrier layer are different from the non-metal dopants of the second gate barrier layer.