IP Library › Granted Patent US 12,463,163
Granted Patent B2
US 12,463,163 · App. 18/544,747 · Granted Nov 4, 2025

Integrated circuit chip including a passivation nitride layer in contact with a high voltage bonding pad and method of making

Inventors: Simone Dario Mariani (Vedano al Lambro, IT); Elisabetta Pizzi (Milan, IT); Daria Doria (Como, IT)
Assignee: STMicroelectronics S.r.l.
H01L24/05H01L21/56H01L24/03H01L24/13H01L24/45H01L2224/02181H01L2224/0219H01L2224/03019H01L2224/0382H01L2224/05582H01L2224/05624H01L2224/05647
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Quick Facts
Patent No.
US 12,463,163
App. No.
18/544,747
Granted
Nov 4, 2025
Kind
B2
Abstract

A back end of line (BEOL) structure for an integrated circuit chip includes a last metal structure providing a bonding pad. A passivation structure over the bonding pad includes a first opening extending exposing an upper surface of the bonding pad. A conformal nitride layer extends over the passivation structure and is placed in contact with the upper surface of the bonding pad. An insulator material layer covers the conformal nitride layer and includes a second opening that extends through both the insulator material layer and the conformal nitride layer. A foot portion of the conformal nitride layer on the upper surface of the bonding pad is self-aligned with the second opening.

Claims (47)

1 . A method, comprising:

depositing a passivation layer over a last metal structure providing a bonding pad;

wherein the last metal structure comprises:

a metal pad at an upper-most metallization layer of a back end of line (BEOL) structure; and

a metal cap finishing structure in contact with an upper surface of the metal pad;

forming a first opening extending through the passivation layer to define a passivation structure and expose an upper surface of the last metal structure;

conformally depositing a nitride layer extending over the passivation structure and in contact with the upper surface of the last metal structure;

coating the nitride layer with an insulator material layer;

forming a second opening extending through the insulator material layer; and

using the insulator material layer with the second opening as a mask to etch through the nitride layer and expose the upper surface of the last metal structure, where a foot portion of the nitride layer on the upper surface of the last metal structure is self-aligned with the second opening.

2 . The method of claim 1 , wherein the passivation layer comprises an oxide layer.

3 . The method of claim 1 , wherein the passivation layer comprises a stack of an oxide layer and a nitride layer.

4 . The method of claim 1 , wherein the last metal structure comprises an Aluminum pad.

5 . The method of claim 1 , wherein the last metal structure comprises a Copper pad.

6 . The method of claim 1 , further comprising:

depositing a stack of insulating layers extending over the upper-most metallization layer;

forming a third opening extending through the stack of insulating layers to expose a portion of the upper surface of the metal pad; and

forming said metal cap finishing structure to extend over an upper surface of the stack of insulating layers.

7 . The method of claim 6 , wherein the stack of insulating layers comprises:

a nitride layer on the top surface of the upper-most metallization layer; and

an oxide layer on top of the nitride layer.

8 . The method of claim 1 , further comprising forming the last metal structure within the BEOL structure of an integrated circuit.

9 . The method of claim 1 , further comprising forming the last metal structure within the upper-most metallization layer of an integrated circuit.

10 . The method of claim 1 , further comprising:

forming a passive circuit component within the BEOL structure of an integrated circuit; and

electrically connecting a terminal of the passive circuit component to the last metal structure.

11 . The method of claim 10 , wherein the passive circuit component is formed in one or more metallization layers of the BEOL structure.

12 . The method of claim 10 , wherein the passive circuit component is one of an inductor or a capacitor.

13 . A method, comprising:

forming a bonding pad in an upper-most metallization layer of a back end of line (BEOL) structure;

forming a last metal structure including a metal cap finishing structure in contact with an upper surface of the bonding pad;

depositing a passivation layer over the last metal structure;

forming a first opening extending through the passivation layer to define a passivation structure and exposing an upper surface of a portion of the last metal structure;

conformally depositing a nitride layer extending over the passivation structure and in contact with the upper surface of the last metal structure;

coating the nitride layer with an insulator material layer;

forming a second opening extending through the insulator material layer, wherein the second opening in insulator material layer leaves a portion of the insulating material layer covering a foot portion of the nitride layer in contact with the upper surface of the last metal structure; and

using the insulator material layer with the second opening as a mask to etch through the nitride layer and expose a portion of the upper surface of the last metal structure so that the insulator material layer and the foot portion are self-aligned.

14 . The method of claim 13 , wherein the passivation layer comprises an oxide layer and/or a nitride layer.

15 . The method of claim 13 , wherein the last metal structure comprises an Aluminum pad or a Copper pad.

16 . The method of claim 13 , further comprising:

depositing a stack of insulating layers extending over the upper-most metallization layer;

forming a third opening extending through the stack of insulating layers to expose a portion of the upper surface of the bonding pad; and

forming the metal cap finishing structure to extend over an upper surface of the stack of insulating layers.

17 . The method of claim 16 , wherein the stack of insulating layers comprises:

a nitride layer on the top surface of the upper-most metallization layer; and

an oxide layer on top of the nitride layer.

18 . The method of claim 13 , further comprising forming the last metal structure within the BEOL structure of an integrated circuit.

Continuity (2)
Division 17391192 · Aug 2, 2021
Related Publication 20240120301A1 · Apr 11, 2024
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