Three-dimensional semiconductor device having vertical misalignment
A multi-stack semiconductor device includes: a lower-stack transistor structure including a lower active region and a lower gate structure, the lower active region including a lower channel structure, and the lower gate structure surrounding the lower channel structure; an upper-stack transistor structure vertically stacked above the lower-stack transistor structure, and including an upper active region and an upper gate structure, the upper active region including an upper channel structure, and the upper gate structure surrounding the upper channel structure; and at least one gate contact plug contacting a top surface of the lower gate structure, wherein the lower gate structure and the upper gate structure have a substantially same size in a plan view, and wherein the lower gate structure is not entirely overlapped by the upper gate structure in a vertical direction.
1 . A multi-stack semiconductor device comprising:
a first transistor structure comprising a first channel structure and a first gate structure on the first channel structure;
a second transistor structure comprising a second channel structure and a second gate structure on the second channel structure, the second transistor being disposed above the first transistor in a first direction; and
a gate contact plug contacting the second gate structure and a top surface of the first gate structure facing a bottom surface of the second gate structure.
2 . The multi-stack semiconductor device of claim 1 , wherein the gate contact plug contacts a side surface of the second gate structure, the side surface being conductive.
3 . The multi-stack semiconductor device of claim 1 , wherein the first gate structure is partially overlapped by the second gate structure in the first direction.
4 . The multi-stack semiconductor device of claim 1 , wherein the first channel structure is partially overlapped by the second channel structure in the first direction.
5 . The multi-stack semiconductor device of claim 1 , wherein the gate contact plug connects the first gate structure to the second gate structure at an outside of the first channel structure and the second channel structure in a plan view.
6 . The multi-stack semiconductor device of claim 1 , wherein the first gate structure and the second gate structure have a substantially same size in a plan view.
7 . The multi-stack semiconductor device of claim 1 , wherein the first channel structure and the second active region have a substantially same size in a plan view.
8 . The multi-stack semiconductor device of claim 1 , wherein the first channel structure comprises a plurality of first nanosheet layers arranged in the first direction, and
wherein the second channel structure comprises a plurality of second nanosheet layers arranged in the first direction or a different type of second channel layer.
9 . The multi-stack semiconductor device of claim 8 , wherein the second transistor is a fin-field effect transistor (FinFET).
10 . A multi-stack semiconductor device comprising:
a first transistor structure comprising a first channel structure and a first gate structure on the first channel structure;
a second transistor structure comprising a second channel structure and a second gate structure on the second channel structure, the second transistor being disposed above the first transistor in a first direction; and
a gate contact plug contacting a top surface of the first gate structure facing a bottom surface of the second gate structure,
wherein the second gate structure is formed to have a predetermined offset with respect to the first gate structure in at least one of a second direction and a third direction in a plan view, and
wherein the first direction intersects the second direction and the third direction, and the second direction intersects the third direction.
11 . The multi-stack semiconductor device of claim 10 , wherein the second gate structure has the predetermined offset only in the second direction among the second direction and the third direction.
12 . The multi-stack semiconductor device of claim 10 , wherein the second channel structure has the predetermined offset with respect to the first active region in at least one of the second direction and the third direction in the plan view.
13 . The multi-stack semiconductor device of claim 10 , wherein the gate contact plug contacts a side surface of the second gate structure.
14 . The multi-stack semiconductor device of claim 10 , wherein the first gate structure and the second gate structure have a substantially same size in a plan view.
15 . The multi-stack semiconductor device of claim 10 , wherein the first channel structure and the second active region have a substantially same size in a plan view.
16 . The multi-stack semiconductor device of claim 10 , wherein the gate contact plug connects the first gate structure to the second gate structure at an outside of the first channel structure and the second channel structure in a plan view.
17 . The multi-stack semiconductor device of claim 1 , wherein the first channel structure comprises a plurality of first nanosheet layers arranged in the first direction, and
wherein the second channel structure comprises a plurality of second nanosheet layers arranged in the first direction or a different type of second channel layer.
18 . The multi-stack semiconductor device of claim 17 , wherein the second transistor is a fin-field effect transistor (FinFET).
19 . A method of forming a multi-stack semiconductor device, the method comprising:
forming a first channel structure and a second channel structure above the first channel structure in a first direction;
forming a first gate structure on the first channel structure;
forming a second gate structure on the second channel structure; and
forming a gate contact plug connecting the second gate structure to a top surface of the first gate structure facing a bottom surface of the second gate structure.
20 . The method of claim 19 , wherein the second gate structure is formed to have a predetermined offset with respect to the first gate structure in at least one of a second direction and a third direction in a plan view, and
wherein the first direction intersects the second direction and the third direction, and the second direction intersects the third direction.